Publications 
Inseok Jung, and Yong-Bin Kim, "A 12-bit 32MS/s SAR ADC Using Built-in Self Calibration Technique To Minimize Capacitor Mismatch ", 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems(DFT), August 3-6, Amsterdam, Netherlands, pp.275-279.
Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Marvin Onabajo, and Yong-Bin Kim, "A Built-In Calibration System with A Reduced FFT Engine for Linearity Optimization of Low Power LNA ", 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems(DFT), August 3-6, Amsterdam, Netherlands, pp221-226.
Inseok Jung and Yong-Bin Kim, "A Novel Self-Calibration Scheme for 12-bit 50MS/s SAR ADC ",2014 IEEE Int'l Midwest Symposium on Circuits & Systems(MWSCAS 2014), August 3-6, College Station, pp. 5-8.
Yongsuk Choi, Chun-hsiang Chang, Hari Chauhan, In-Seok Jung, Marvin Onabajo, and Yong-Bin Kim,, "A Built-In Calibration System to Optimize Third-Order Intermodulation Performance of RF Amplifiers ", 2014 IEEE Int'l Midwest Symposium on Circuits & Systems(MWSCAS 2014), August 3-6, College Station, TX, pp. 599-602.
Haiyang Zhu, Wenhua Yang, Nathan Egan, and Yong-Bin Kim, "Calibration Technique Tracking Temperature for Current-Steering Digital-to-Analog Converters ", 2014 IEEE Int'l Midwest Symposium on Circuits & Systems(MWSCAS 2014), August 3-6, College Station, TX, pp.1-4.
Ho Joon Lee, Yong-Bin Kim, and Kyung Ki Kim,, "Full Custom Implementation of a S-Box Circuit Architectue Using Power Gated PLA Structure ", 2014 IEEE Int'l Midwest Symposium on Circuits & Systems(MWSCAS 2014), August 3-6, College Station, TX, pp. 294-297.
Yongsuk Choi and Yong-Bin Kim, "A Mixed-Signal Self-Calibration Technique for Baseband Filters in System-On-Chip Mobile Transceivers ", 2014 ACM GLSVLSI Conference(GLSVLSI 2014), May 21-23, Houston, Texas, pp.312-316.
Hojoon Lee and Yong-Bin Kim, "An Area Efficient Low Power High Speed S-Box Implementation Using Power-Gated PLA ", 2014 ACM GLSVLSI Conference(GLSVLSI 2014), May 21-23, Houston, Texas, pp. 93-94.
Jing Lu and Yong-Bin Kim, "A Low Power High Resolution Digital PWM with Process and Temperature Calibrations for Digital Controlled DC-DC Converters ", 2014 ACM GLSVLSI Conference(GLSVLSI 2014), May 21-23, Houston, Texas, pp.75-76.
Jun Wu,Hengsi Qin, Yiyu Shi, Minsu Choi, Ho Joon Lee, Kyug Ki Kim, and Yong-Bin Kim, "Stochastic Encoding for Enhanced Resistance against Power Analysis Attacks in Crypto-Hardware", 2014 IEEE International Industrial Information Systems Conference(IIISC 2014), Jan 21-24, Chiang Mai, Thailand, pp.7-9.
Inseok Jung and Yong-Bin Kim, "Test Methodology using Parametric Measurement Unit for Automated Test Equipment Systems with 600MHz High Speed DCL", 2014 IEEE International Industrial Information Systems Conference(IIISC 2014), Jan 21-24, Chiang Mai, Thailand, pp.17-19.
Jing Lu, Jing Yang, and Yong-Bin Kim, "Implementation of CMOS Neuron for Robot Motion Control Unit", 2013 IEEE International SoC Conference (ISOCC), Nov. 17-19, 2012, Busan South Korea, pp. 9-11.
Weifu Li and Yong-Bin Kim, "A High Performance Modulo 2n+1 Squarer Design Based on Carbon Nanotube Technology", 2013 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.4-7, 2013, Columbus OH, pp. 429-432.
Inseok Jung, Marvin Onabajo, and and Yong-Bin Kim, "A 10-bit 64MS/s SAR ADC Using Variable Clock Period Method", 2013 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.4-7, 2013, Columbus OH, pp. 1144-1147.
Yongsuk Choi,Heungjun Jeon, and Yong-Bin Kim, "A Switched-Capacitor DC-DC Converter Using Delta-Sigma Digital Pulse Frequency Modulation Control Method", 2013 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.4-7, 2013, Columbus OH, pp. 356-359.
Ho Joon Lee and Yong-Bin Kim, "Low Power Null Convention Logic Circuit Design Based on DCVSL", 2013 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.4-7, 2013, Columbus OH, pp.29-32.
Inseok Jung and Yong-Bin Kim, "Test Methodology Using Parametric Measurement Unit for Automated Test Equipment Systemss with 600MHz High Speed DCL", 2013 IEEE North Atalantic Test Workshop (NATW), May.8-10, 2013, Wakefield, MA, 4.1
Hari Chauhan, Yongsuk Choi, Chun-hsiang, Yong-Bin Kim, and Marvin Onabajo, "On-Chip Amplifier Linearity Calibration with the Fast Fourier Transform", 2013 IEEE North Atalantic Test Workshop (NATW), May.8-10, 2013, Wakefield, MA, 4.4.
Hari Chauhan, Yongsuk Choi, Inseok Jung, Chun-hsiang, Marvin Onabajo, and Yong-Bin Kim, "On-Chip Spectral Analysis for Built-In Testing and Digital Calibration of Analog Integrated Circuits", 2013 Northeastern Research, Innovation, and Schlarship Expo (RISE:2013), March.22, 2013, Boston, MA, Abstract ID# 122.
Edward Collins, Inseok Jung, and Yong-Bin Kim, and Kyung Ki Kim, "A Design and Integration of Parametric Measurement Unit on to a 600MHz DCL", 2012 IEEE SoC Design Conference(ISOCC), Nov.4-7, 2012, Jeju, South Korea. pp435-438.
Jianping Gong, Jie Han,Yong-Bin Kim, F. Lombardi, and Jie Han, "Hardening a Memory Cell for Low Power Operation by Gate Leakage Reduction", 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct.3-5, 2012, Austin, Texas, pp73-78.
Jin Wu, Yong-Bin Kim, and Minsu Choi, "Configurable Logic Block (CLB) Design for Asynchronous Nanowire Crossbar System", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 170-173.
Jin Wu, Yong-Bin Kim, and Minsu Choi, "Configurable Logic Block (CLB) Design for Asynchronous Nanowire Crossbar System", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 170-173.
Ho Joon Lee, Yong-Bin Kim, and Kyung Ki Kim, "On-Chip HBD Sensor for Nanoscale CMOS Technology", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 434-457.
Siva Pavan Kumar Kotipalli, Kyung Ki Kim, Yong-Bin Kim, and Minsu Choi, "Design and Evaluation of Side Side Channel Attacck Resistant Asynchronous AES Round Function", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 410-413.
Jing Lu, Jing Yang,Yong-Bin Kim, and Joseph Ayers, "Low Power, High PVT Variation Tolerant Central Pattern Generator Design for a Bio-hybrid Micro Robot", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 782-785.
Yongsuk Choi,Yong-Bin Kim, and Fabrizio lombardi, "Soft Error Masking Latch for Sub-Threshold Voltage Operation", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 25-28.
Moon Seok Kim, Yong-Bin Kim, and Kyung Ki Kim, "All-Digital Phased-Locked Loop with Local Passive Interpolation Time-to-Digital Converter Based on a Tristate Inverter", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 326-329.
He Qe,Yong-Bin Kim, and Minsu Choi, "A High Speed Low Power Modulo 2^n+1 Multiplier Design Using Carbon-nanotube Technology", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 406-409.
Heungjun Jeon and Yong-Bin Kim, and Kyung Ki Kim, "A Novel 4-to-3 Step-Down On-Chip SC DC-DC Converter With Reduced Bottom-Plate Loss", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 1060-1063.
Inseok Jung and Yong-Bin Kim, and F. Lombardi, "A Novel Sort Error Hardened 10T SRAM Cells for Low Voltage Operation", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 714-717.
Jin Wu, Yong-Bin Kim, and Minsu Choi, "Post-Configuration Repair Strategy for Asynchronous Nanowire Crossbar System", 2012 IEEE International Midwest Symposium on Circuits and Systems(MWCAS), Aug.5-8, 2012, Boise Idaho, pp. 174-177.
Heung Jun Jeon and Yong-Bin, "A Fully Integrated Switched-Capacitor DC-DC Con- verter with Dual Output for Low Power Application", 2012 ACM Great Lakes Symposium on VLSI(GLSVLSI),( GLSVLSI 2012), May 3-4, 2012, Salt Lake City, Utah, pp.83-86.
In-Seok Jung and Yong-Bin, "A Low Stand-by Power Start-up Circuit for SMPS PWM Controller", 2012 ACM Great Lakes Symposium on VLSI(GLSVLSI),( GLSVLSI 2012), May 3-4, 2012, Salt Lake City,Utah, pp.251-254.
Jing Yang and Yong-Bin, "Self Adaptive Body Biasing Scheme For Leakage Power Reduction In Nanoscale CMOS Circuit", 2012 ACM Great Lakes Symposium on VLSI(GLSVLSI),( GLSVLSI 2012), May 3-4, 2012, Salt Lake City,Utah, pp. 111-115.
Edward Collins, Inseo Jung, Yong-Bin Kim, and Kyung Ki Kim, "A Design Approach of a Parametric Measurement Unit on to a 600MHz DCL", International SoC Design Conference( ISOCC 2011), November 17-18, 2011, Jeju, Korea, 2011, pp.446-449.
Sheng Lin, Yong-Bin Kim, and Fabrizio Lombardi, "A 13T 32nm CMOS Memory Cell for Hardening to a Single Event with Multiple Node Upset", IEEE International Conference on Computer Design(ICCD), Amherst, MA, October 9-12, 2011, pp. 320-325.
Tina Rookmaaker, Moonseok Kim, and Yong-Bin Kim, "Design and Analysis of a Quad-ferential Amplifier", IEEE International Midwest Symposium on Circuits and Systems(MWSCAS), Seoul, South Korea, August 2011, Wp1A-4(01-1055).
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Jing Lu, Yong-Bin Kim, and Joseph Ayers, "A Low Power 65nm CMOS Electronic Neuron and Synapse Design for a Biomimetic Micro-Robot", IEEE International Midwest Symposium on Circuits and Systems(MWSCAS), Seoul, South Korea, August 2011, Tp1B-1(01-1099).
Daniel Debolt, Yong-Bin Kim, and Joseph Ayers, "Scaling Issues for VLSI Implementations of Biologically Accurate Neurons and Central Pattern Generators", 2011 IEEE International SoC Design Conference(ISOCC 2011), Jeju, South Korea, November 17-18, 2011(Submitted).
Heung Jun Jun, Yong-Bin Kim, and Minsu Choi, "Offset Voltage Analysis of Dynamic Latched Comparator", IEEE International Midwest Symposium on Circuits and Systems(MWSCAS), Seoul, South Korea, August 2011, Ta1A01(01-1028).
Inseok Jung, Yong-Bin Kim, and Minsu Choi, "The Novel Switched-Capacitor DCDC Converter for Fast Response and Reduced Ripple", IEEE International Midwest Symposium on Circuits and Systems(MWSCAS), Seoul, South Korea, August 2011, Wa1I-4(04-1006).
Chunchun Sui, Jun Wu, Yiyu Shi, Yong-Bin Kim, and Minsu Choi, "Random Dynamic Voltage Scaling Desgin to Enhance Security of NCL S-Box", IEEE International Midwest Symposium on Circuits and Systems(MWSCAS), Seoul, South Korea, August 2011, Wp1G-1(02-1021).
Veeresh Hongal, Raghavendra Kotikalapudi, Yong-Bin Kim, and Minsu Choi, "A Novel Divide and Conquer Testing Technique for Memristor Based Lookup Table", IEEE International Midwest Symposium on Circuits and Systems(MWSCAS), Seoul, South Korea, August 2011, Tp1G-3(05-1013).
Sheng Lin, Yong-Bin Kim, and Fabrizio Lombardi, "A 13T CMOS Hardened Memory Cell for Tolerance to a Single Event with Multiple Node Upsets", 2011 IEEE Test Conference, Sep., 2011, Anaheim, CA(Submitted).
Rui Tang, Kyung Ki Kim, and Yong-Bin Kim, "Eight Phase VCO Design Using Carbon Nano-tube Transistor", 2010 IEEE International SOC Conference, Nov., 2010, Incheon, South Korea, pp.400-403.
Geun Ho Cho, Yong-Bin Kim, and F. Lombardi, "Modeling a CNTFET with Undeposited CNT Defects", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , Oct. 6-8,2010, Kyoto, Japan,pp.289-296.
Young Bok Kim and Yong-Bin Kim, "High Speed and Low Power Transceiver Design with CNFET and CNT Bundle Interconnect", IEEE International SOC Conference, Sep. 27-29,2010, Las Vegas, NV,pp.152-157.
Heung Jun Jeon and Yong-Bin Kim, "A CMOS Low-Power Low-Offset and High-Speed Fully Dynamic Latched Comparator", IEEE International SOC Conference, Sep. 27-29,2010, Las Vegas, NV, pp.285-288.
Jiaping Hu, Yong-Bin Kim,and Joseph Ayers, "A CMOS Low-Power Low-Offset and A 65nm CMOS Ultra Low Power and Low Noise 131M Ohm Front-End Transimpedance Amplifier", IEEE International SOC Conference, Sep. 27-29, 2010, Las Vegas, NV, pp.281-284.
Rajashekhar Modugu,Yong-Bin Kim, and Minsu Choi, "Design and Performance Measure-ment of Efcient IDEA (International Data Encryption Algorithm) Crypto-Hardware using Novel Modular Arithmetic Components", IEEE IMTC(Instrumentation and Measurement Technology Conference), May 3-6, 2010, Austin, TX, pp.1222-1227.
HeungJun Jeon and Yong-Bin Kim, "Offset Voltage Analysis of Dynamic Latched Comparator", 2010 Midwest Symposium on Circuits and Systems, Seattle, WA, pp.541-544.
Janardhanan Ajit and Yong-Bin Kim, " Ultra Low-Voltage Delay Locked Loop Using Carbon Nanotubes", 2010 Midwest Symposium on Circuits and Systems, Seattle, WA. pp.753-756.
Young Bok Kim and Yong-Bin Kim, "Design and Noise Analysis of 8Gb/s Capacitive Low Power and High Speed 4-PWAM Tranceiver", 2010 Midwest Symposium on Circuits and Systems, Seattle, WA, pp.785-788.
Dipen Patel and Yong-Bin Kim, " Carbon Nanotube Bundle Interconnect: Performance Evaluation, Optimum Repeater Size an Insertion for Global Wire", 2010 Midwest Symposium on Circuits and Systems, Seattle, WA, pp.749-752.
Jiaping Hu and Yong-Bin Kim, " A Low Power 100M Ohm CMOS Front-End Transimpedance Amplifier for Biosensing Applications", 2010 Midwest Symposium on Circuits and Systems, Seattle, WA, pp.541-7543.
Young Bok Kim, Yong-Bin Kim, and Fabrizio Lombardi, "8Gb/s Capacitive Low Power and High Speed 4-PWAM Tranceiver Design", 2010 Great Lakes Symposium on VLSI(GLSVLSI), Providence, RI, pp.33-36.
Jun Wu, Yong-Bin Kim, and Minsu Choi, " Low Power Side-Channel Attack-Resistant Asynchronous S-Box Design for AES Cryptosystems", 2010 Great Lakes Symposium on VLSI(GLSVLSI), Providence, RI, pp.459-462.
Janardhanan Ajit and Yong-Bin Kim, "Performance of Analog Circuits with Carbon Nanotube FET", 2010 Great Lakes Symposium on VLSI(GLSVLSI), Providence, RI, pp.163-166.
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Jun Zhao and Yong-Bin Kim, "A Novel All Digital Fractional-N Frequency Synthesizer Architecture with Fast Acquisition and Low Spur", 2010 International Symposium on Quality Electronic Design(ISQED), March 22-24, 2010, San Jose, CA, pp.99-102.
Heung Jeon Jun and Yong-Bin Kim, "A Low-offset High-speed Double-tail Dual-rail Dynamic Latched Comparator", 2010 Great Lakes Symposium on VLSI(GLSVLSI), Providence, RI, pp.45-48.
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Sheng Lin, Yong-Bin Kim, and Fabrizio Lombardi, "Read-Out Schemes for a CNTFET-based Crossbar Memory", 2010 Great Lakes Symposium on VLSI(GLSVLSI), Providence, RI, pp.167-170.
Young Bok Kim, Yong-Bin Kim, and Fabrizio Lombardi, "A Universal Gate for Combinational Design of QCA Circuits", IEEE International,SoC Design Conference November, 2009, Busan, South Korea(Invited paper), pp.92-95.
Young Bok Kim, Yong-Bin Kim, and Fabrizio Lombardi, "Error Tolerant DNA Self-Assembly by Link-Fracturing", IEEE International,SoC Design Conference November, 2009, Busan, South Korea, pp75-78.
X. Ma, M. Hashempour, Yong-Bin Kim, and Fabrizio Lombardi, "Errors in DNA Self-Assembly By Synthesized Tile Sets", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Ocotober, 2009, Chicago, IL, pp. 112-120.
Yong-Bin Kim, "The New Paradigm of the High Performance and Low Power Full Custom Design Method Based on Nanotechnology", IEEE Workshop on Unique Chips and Systems 2009(UCAS-5), April 26, 2009, Boston, MA, pp. 1-4.
Sheng Lin, Yong-Bin Kim, and Fabrizio Lombardi, "A Novel Hardened Design of a Memory Cell in Nanoscale CMOS", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Ocotober, 2009, Chicago, pp. 58-64.
Young Bok Kim, Yong-Bin Kim, and F. Lombardi, "A Novel Design Methodology to Optimize The Speed and Power of the CNFET Circuits ", MWSCAS 2009(IEEE International Midwest Symposium on Circiuts and Systems), August 2-5, 2009, Cancun, Mexico, pp.1130-1133.
Geun Ho Cho, Yong-Bin Kim, and F. Lombardi "Assessment of the CNFET Based Circuit Performance and Robustness to PVT Variation", MWSCAS 2009(IEEE International Midwest Symposium on Circiuts and Systems), August 2-5, 2009, Cancun, Mexico, pp.1106-1109.
Jun Zhao, Yong-Bin Kim, "A Novel ALL-Digital Phase Locked Loop With Ultra Fast Frequency and Phase Acquisition ", MWSCAS 2009(IEEE International Midwest Symposium on Circiuts and Systems), August 2-5, 2009, Cancun, Mexico, pp.487-490.
Sheng Lin, Yong-Bin Kim, and F. Lombardi " Novel Design Technique for Soft Error Hardening of Nanoscale CMOS Memory ", MWSCAS 2009(IEEE International Midwest Symposium on Circiuts and Systems), August 2-5, 2009, Cancun, Mexico, pp.679-682.
Sheng Lin, Yong-Bin Kim, and F. Lombardi "A Novel CNTFET Based Ternary Logic Gate Design ", MWSCAS 2009(IEEE International Midwest Symposium on Circiuts and Systems), August 2-5, 2009, Cancun, Mexico, pp.435-438.
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi, "Soft-Error Hardening Designs of Nanoscale CMOS Latches", IEEE VLSI Test Symposium 2009, May 3-7,2009, Santa Cruz, CA, pp. 41-46.
Geunho Cho, Yong-Bin Kim, Fabrizio Lombardi, "Performance Evaluation of CNFET-Based Logic Gatesr", IEEE International Instrumentation and Measurement Technology Conference(I2MTC), May.5-7, 2009, Singapore, pp. 909-912.
HeungJun Jeon, Yong-Bin Kim, "A Novel Technique to Minimize Standby Leakage Power in Nanoscale CMOS VLSI", IEEE International Instrumentation and Measurement Technology Conference(I2MTC), May.5-7, 2009, Singapore, pp. 1372-1375.
Shikha Chaudhary, Minsu Choi, and Yong-Bin Kim "Probabilistic Analysis of Design Mapping in Asynchronous Nanowire Crossbar Architecture ", IEEE International Instrumentation and Measurement Technology Conference(I2MTC), May.5-7, 2009, Singapore, pp. 1116-2000.
Jun Zhao and Yong-Bin Kim, "`A Novel Digital Phase-Locked Loop with Fast Acquisition and Low Jitter", IEEE International SoC Design Conference(ISOCC), Nov.24-25, 2008, Pusan, South Korea, pp. 277-280.
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi, and Young Jun Lee, "A Low Power 8T SRAM Cell Design technique for CNFET", IEEE International SoC Design Conference(ISOCC), Nov.24-25, 2008, Pusan, South Korea, pp. 176-179.
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi, and Young Jun Lee, "A New SRAM Cell Design Using CNTFET", IEEE International SoC Design Conference(ISOCC), Nov.24-25, 2008, Pusan, South Korea, pp. 168-171.
S. Frechette, Yong-Bin Kim, and F. Lombardi, "Checkpointing of Rectilinear Growth in DNA Self-assembly", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 1-3. 2008, Cambridge, Massachussets, pp. 525-533.
Sheng Lin, Yong-Bin Kim, and F. Lombardi, "A Highly-Stable Nanometer Memory for Low Power Design", IEEE International Workshop on Design and Test of Nano Device, Circuits, and Systems(NDCS'08), September 20-30. 2008, Boston, Massachussets, pp. 17-20.
Young Bok Kim, Yong-Bin Kim, and F. Lombardi, "New SRAM Cell Design for Low Power and High Reliabilty Using 32nm Independent Gate FinFET Technology ", IEEE International Workshop on Design and Test of Nano Device, Circuits, and Systems(NDCS'08), September 20-30. 2008, Boston, Massachussets, pp. 25-28.
Sheng Lin, Yong-Bin Kim, and F. Lombardi, "1 Low Leakage 9T SRAM cell for Ultra-Low Power Operation", ACM GLSVLSI'08(Great Lake Symposium on VLSI), May 4-6, 2008, Orlando, Florida, pp.123-126.
Young Bok Kim, Yong-Bin Kim, and F. Lombardi, "A Technique for Low Power Dynamic Circuit Design in 32nm Double Gate FinFET Technology", IEEE International MWSCAS 2008, August 10-13, 2008, Knoxville, Tenesse, pp. 779-782.
Sheng Lin, Yong-Bin Kim, and F. Lombardi, "A 32nm SRAM Design for Low Power and High Stability", IEEE International MWSCAS 2008, August 10-13, 2008, Knoxville, Tenesse, pp. 422-425.
Jun Zhao and Yong-Bin Kim, "A 12-bit Digitally Controlled Oscillator with Low Power Consumption and Low Jitter", IEEE International MWSCAS 2008, August 10-13, 2008, Knoxville, Tenesse, pp.370-373.
Young Bok Kim, Yong-Bin Kim, and F. Lombardi, "Low Power 8T SRAM Using 32nm Independent Gate FinFET Technology ", IEEE International SOC Conference, Sep. 17-20, 2008, Newport Beach, California, pp. 247-250.
Jun Zhao and Yong-Bin Kim, "A Low Power 32 Nano Meter CMOS Digitally Controlled Oscillator ", IEEE International SOC Conference, Sep. 17-20, 2008, Newport Beach, California, pp. 183-186.
Youong Bok Kim and Yong-Bin Kim, "Fault Tolerant Source Routing for Network-on-chip", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2007, September 26-28, 2007, Rome, Italy, pp.12-20.
Ravi Bonam, Yong-Bin Kim, and Minsu Choi,, "Defect Tolerant Gate Macro Mapping and Placement in Clock-Free Nanowire Crossbar Architecture'", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2007, September 26-28, 2007, Rome, Italy, pp.161-169.
Kyung Ki Kim and Yong-Bin Kim, "Phase-Locked Loop Considering Leakage and Power/Ground Noise", IEEE International SoC Design Conference(ISOCC), October 15-16, 2007, Seoul, Korea, pp.295-298.
Ping Liu and Yong-Bin Kim, "An Accurate Analytical Propagation Delay Model of Nano CMOS Circuits", IEEE International SoC Design Conference(ISOCC), October 15-16, 2007, Seoul, Korea, pp.200-203.
Ping Liu and Yong-Bin Kim, "An Accurate Timing Model for Nano CMOS Circuit Considering Statistical Process Variation", IEEE International SoC Design Conference(ISOCC), October 15-16, 2007, Seoul, Korea, pp.269-272.
Joseph Ayers, Nikolai Rulkov, Dan Knudsen, Yong-Bin Kim, Alexander Volkovskii, Allen Selverston, "Controlling Underwater Robots with Electronic Nervous Systems", IEEE International Conference on Robotics and Automation(ICRA) 2007, April 10-14, 2007, Rome, Italy,TF-1, pp. 1-6.
Yong-Bin Kim and James Doyle, " A CMOS CORDIC Processor Design for Wireless Telecommunication ", IEEE Midwest Symposium on Circuit and Systems(with NEWCAS), August 5-8, 2007, Montreal, Canada, pp.1336-1339.
Jun Zhao and Yong-Bin Kim, " Circuit Implementation of FitzHugh-Nagumo Neuron Model Using Field Programmable Analog Array'' ",IEEE Midwest Symposium on Circuit and Systems(with NEWCAS), August 5-8, 2007, Montreal, Canada, pp.772-775.
Kyung Ki Kim, Yong-Bin Kim, ""Probabilistic Leakage Power Estimation of Partially-Depleted Silicon-On-Insulator(SOI) Gates," IEEE Midwest Symposium on Circuit and Systems(with NEWCAS), August 5-8, 2007, Montreal, Canada, pp.980-983.
Rui tang, Yong-Bin Kim, ""Energy Efficient CMOS PWAM Transmitter Design," IEEE Midwest Symposium on Circuit and Systems(with NEWCAS), August 5-8, 2007, Montreal, Canada, pp.1161-1164.
Yong-Bin Kim and James Doyle, " A Low Power Digital Self-Adjusting Adaptive Voltage Scaling System Considering PVT and Loading Variations ", IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007.
Yong-Bin Kim and Kyung Ki Kim, " Optimal Body Biasing for Minimum Leakage Power in Standby Mode ", IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007, pp.1161-1164.
Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi,'' Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer'', Design Automation and Test in Europe, April 16-20,2007 Acropolis Nice, France, pp. 847-852.
Byunghyun Jang, Yong-Bin Kim, '' Modeling and Evaluation of Multi-Bank SRAM Design for Leakage Power Reduction'', 2007 Boston Area Architecture(BARC) Workshop, January 26 2007, Booston, MA, pp15-26.
Youngbok Kim, Yong-Bin Kim, '' An Asynchronous NoC Router Architecture Supporting Quality-of-Service'', 2007 Boston Area Architecture(BARC) Workshop, Januray 26 2007, Booston, MA, pp17-18.
Kyung Ki Kim, Jing Huang, Rui Tang, Yong-Bin Kim, and Fabrizio Lombardi, Minsu-Choi "" Analysis and Simulation of Jitter for High Speed Links in Systems-On-Chip Systems ", IMTC 2007 IEEE Instrumentation and Measurement Technology Conference, May 1-3, 2007, Warsaw, Poland, pp.1-4.
Kyung Ki Kim, Jing Huang, Rui Tang, Yong-Bin Kim, and Fabrizio Lombardi, "" Accurate Macro-Modeling for Leakage Current for I(DDQ) Test ", IMTC 2007 IEEE Instrumentation and Measurement Technology Conference, May 1-3, 2007, Warsaw, Poland, pp.1-4.
Josepth Ayers, Nikolai Rulkov, Edward Taub, Yong-Bin Kim, Allen Selverston, Gittendra Uswatte ``Electronic Neurons From Biomimetic Robots to Blast Neuroehabilitation", Seventh International Symposium on Technology and Mine Problem, May. 2-5, 2006, Monterey, CA, Chapter B-3.
Yong-Bin Kim` ` Quantum-Dot Cellular Automata SPICE Macro Model", Global Convention of Ethnic Korean Scientists and Engineers 2006'', Seoul, Korea, July 17-22, 2006, pp171.
Rui Tang, Yong-Bin Kim, ""A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits, ", IEEE SOCC'06(IEEE International SOC Conference), September 24-27, 2006, Austin, Texas, pp.119-122.
Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, "" A Load board Design Using Compound Dot Technique and Phase Detector for Hierarchy ATE Calibrations, "IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Washinton DC, October 4-6, 2006, pp486-494.
Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim, "" Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects, "IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Washinton DC, October 4-6, 2006, pp98-106.
Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi "" Error Tolerance of DNA Self-Assembly by Monomer Concentration Control ", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Washinton DC, October 4-6, 2006, pp89-97.
Rui Tang and Yong-Bin Kim, "" PWAM Signaling Scheme for High Speed Serial Link Tranceiver Design ", ACM GLSVLSI'06(Great Lake Symposium on VLSI), Philadelphia, PA, April 30-May 2 2006, pp.49-52.
Kyung Ki Kim and Yong-Bin Kim, "" Ultra Low Voltage VCO Design Using Schmitt Trigger on SOI(Silicon On Insulator) ", IEEE ISOCC'06(IEEE International SOC Conference), October 26-27, 2006, Seoul South Korea, pp127-130.
Rui Tang, Yong-Bin Kim, Minsu Choi and Fabrizio Lombardi, ""Jitter Analysis in High Speed Serial Link Using a PWM Scheme ", IEEE IMTC(Instrumentation and Measurement Technology Conference) 2006, October 2006, Sorrento, Italy, pp.494-497.
Kyung Ki Kim, Yong-Bin Kim, N. park, and F. Lombardi, "" Clock Grid Simulation Using Transient S-parameter Modeling", IEEE IMTC(Instrumentation and Measurement Technology Conference) 2006, October 2006, Sorrento, Italy, pp.225-228.
Kyung Ki Kim, Yong-Bin Kim, N. park, and F. Lombardi, ""Statistical Characterization of Partially-Depleted SOI Gates'", IEEE IMTC(Instrumentation and Measurement Technology Conference) 2006, October 2006, Sorrento, Italy, pp.245-248.
Joseph Ayers, Nikolai Rulkov, Yong-Bin Kim, Alexander Volkovskii, and Allen Selverston, ""Hybrid Neuronal Architectures for Biomimetic Robot Controller", IEEE International Conference on Robotics and Automation(ICRA) 2006, May 15-19, 2006, Orlando, Florida.
Young Jun Lee, Dae Woon Kang, Jim Doyle, and Y. Kim, "A Sub-1V Power Supply Sub-bandgap with an Extended Voltage and Temperature Range", IEEE International SoC design Conference(ISOCC), October 20-21, 2005, Seoul, South Korea, pp79-82.
J. Ayers, N. Rulkov, Y. Kim, A. Volkovski, and A. Selverston, "Hybrid Neuronal Architectures for Biomimetic Robot Controllers'', SfN(Society for Neuro Science), November 12-16, 2005, Washington DC, program number 753.18.
Rui Tang, Y.B. Kim, "A Novel Delay Balancing Algorithm for Wave Pipelined Circuits'', IEEE International Symposium on Circuits and Systems(MWSCAS), August 7-10, 2005, Cincinnati, OH, pp. 1035-1038.
Rui Tang, Bart McDanniel, Yong-Bin Kim, "A Power Optimization Method for SiGe Butterworth Filter Design'', IEEE International Symposium on Circuits and Systems(MWSCAS), August 7-10, 2005, Cincinnati, OH, pp.1633-1636.
Young Jun Lee, Jihyun Lee, and Yong-Bin Kim, "Low Power CMOS Adaptive Electronic Central Pattern Generator Design'', IEEE International Symposium on Circuits and Systems(MWSCAS), August 7-10, 2005, Cincinnati, pp. 1350-1353.
Kyungki Kim, J. Hwang, Y.B. Kim, and F. Lombardi, "On Modeling and Analysis of Jitter in ATE Using MATLAB'', IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, October 3-5, 2005, pp285-293.
Kyungki Kim, J. Hwang, Y.B. Kim, and F. Lombardi, "Data Dependent Jitter (DDJ) Characterization Methodology'', IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, October 3-5, 2005, pp294-302.
B.Jang, M. Choi, N.Park, Y. Kim,V. Piuri, F. Lombardi, "Spare Line Borrowing Technique for Distributed Memory Cores in SoC'', IEEE IMTC(Instrumentation and Measurement Technology Conference) 2005, Ottawa, Canada, May 16-19 2005, vol.1, pp.43-48.
Woo Jin Kim and Y. Kim, "Wave Pipelined Circuits Synthesis'' IEEE IMTC(Instrumentation and Measurement Technology Conference) 2005, Ottawa, Canada, May 16-19 2005, vol.1, pp.32-46.
Duong Tran, Kyong Ki Kim, and Y. Kim, "Power Estimation in Digital CMOS VLSI Chips'', IEEE IMTC(Instrumentation and Measurement Technology Conference) 2005, Ottawa, Canada, May 16-19 2005, vol.1, pp.317-321.
Rui Tang, Fengming Zhang, and Y. Kim, "Quantum-Dot Cellular Automata SPICE Macro Model'' ACM GLSVLSI'05(Great Lake Symposium on VLSI), Chicago, IL, April 17-19 2005, pp108-111.
Daw Woon Kang, Y. Kim, J. Doyle, Mark Hartman, Sandeep Dhar, Marty B. Dermody, Robert C. Woolf, Ravindra S. Ambatipud, "A Low Powered Methodology for Portable Electronics '',International Symposium of Advanced Radio Technologies, March 1-3 2005, Denver CO, pp.109-116.
T. Feng, N. Park, Y. Kim, F. Lombardi, and F. Meyer, "Reliability Modeling and Assurance of Clockless Wave Pipeline'', IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cannes, France, October 10-13 2004, pp.442-450.
T. Feng, B. Jin, J. Wang, N. Park, Y.B. Kim, and F. Lombardi,"Fault Tolerant Clockless Wave Pipeline Design'' ACM Conference on Computing Fronteers(CF), May 2004, Ischia, Italy, pp.350-356.
F. Zhang, R. Tang , and Y. B. Kim, "SET-Based Nano-Circuit Simulation and Design Method Using HSPICE", IEEE GLSVLSI(Great Lake VLSI Symposium) April 2004, Boston, MA, pp.344-34.
Y.J.Lee, Jihyun Lee, Y.B. Kim, J. Ayers, "Low Power Real Time Electronic Neuron VLSI Design Using Sub-threshold Technique'', IEEE International Symposium on Circuits and Systems(ISCAS), May 23-26, 2004, British Columbia, Canada, Vol IV, pp.744-747.
J. H. Lee, Y. J. Lee and Y. B. Kim, "SRAM Word-oriented Redundancy Methodology using Built In Self-Repair'' IEEE ASIC/SoC Conference, Sep 12-15, 2004,Santa Clara,USA, pp.219-222.
Y. J. Lee, J. H. Lee, J. Y. Heo, F. Zhang and Y. B. Kim, "Test Methodology for Low Power VLSI Neural Oscillator Circuit'', IMTC 2004 IEEE Instrumentation and Measurement Technology Conference, May 18-20, 2004, Como, Italy, pp.1546-1550.
Y. J. Lee, N. Park and Y. B. Kim, "Timing Requirement for Reliable Latch Based Circuit'', IMTC 2004 IEEE Instrumentation and Measurement Technology Conference, May 18-20,2004.
Ottavi and Y.B.Kim, "Yield Estimation Method of SRAM Array'', IMTC 2004 IEEE Instrumentation and Measurement Technology Conference, May 18-20,2004
L. Schiano, M. Momenzadeh, F.Zhang, Y. J. Lee, Y. B. Kim, F. J. Meyer, F. Lombardi, S. Max, "Frequency Domain Measurement of Timing Jitter in ATE", 2004 IEEE Instrumentation and Measurement Technology Conference, May 18-20 2004, Como, Italy, pp.2150-2155.
L. Shiano, Y. Kim, F. Lombardi, "Scan Test IP Cores in an ATE Environment'', IEEE Electronic, Design, Test, and Application(Delta) Conference, Jan 28-30, 2004,Perth Australia, pp.281-286.
Woo Jin Kim, and Y.B. Kim, "Applying Automation to Wave Pipelined Circuits'', IEEE GLVLSIS(Great Lake VLSI Symposium) April 2004,Boston,MA, U.S.A.
Young Joon Lee and Y. Kim, "A Fast and Precise Estimation Method of Crosstalk Noise", IEEE International Symposium on Circuits and Systems(ISCAS),), May 23-26, 2004,British Columbia,Canada, Vol II, pp.873-876.
B. Jin, T. Feng, N. Park, K.M. George, F. Lombardi, Y.B. Kim, " Off-Device Falut Tolerance for Digital Imaging Devices'', IMTC(IEEE Instrumentation and Measurement Technology Conference), May 18-20, 2004,Como,Italy, pp.627-632.
Woo Jin Kim and Y. Kim, "Automating the Design Approach to Wave Pipelined Circuits'', IEEE Design and Test of Computers'', Nov/Dec 2003, pp.51-58.
Soha Hassoun, Y. Kim, and F. Lombardi, "Introduction: Clockless Digital VLSI Circuit'', IEEE Design and Test of Computers'', Nov/Dec 2003, pp.5-8.
F.-M. Zhang, Y.-J. Lee, T. Kane, L. Schiano, M. Momenzadeh, Y. Kim, F. J. Meyer, F. Lombardi, S. Max, P. Perkins, "A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment'', IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT'03), Nov.3-5, 2003 Cambridge, MA, USA, pp.159-166.
T.Feng, N. Park, Yong-Bin Kim, V.Piuri, "Yield Modeling and Analysis of A Clockless Asynchronous Wave Pipeline with Pulse Faults'',IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT'03), Nov.3-5, 2003 Cambridge, MA, USA, pp.34-41.
Woo Jin Kim, and Y. Kim, "Clocking for Correct Functionality on Wave Pipelined Circuits'', IEEE International ASIC/SOC Conference 2003,Portlanad, OR, Sep.17-20, 2003, pp.261-264.
T. Doyle, Wilsch, Young Jun Lee, and Y.Kim, "Implementation of 1V Supply Voltage CMOS Subbandgap Reference Circuit '', IEEE International ASIC/SOC Conference, Sep 17-20, 2003Portalnad,OR, pp.323-326.
M. Choi, N. park, F. Lombardi, Y. Kim, V. Piuri, "Optimal Spare Utilization in Repairable and Reliable Memory Cores'', 2003 IEEE International Workshop on Memory Technology, Design and Testing(MTDT-03), July 28-29, 2003,San Jose, CA,USA, pp.64-71.
James T. Doyle, Young Jun Lee, Yong-Bin Kim, "An Accurate DAC Modeling Technique Based on Wavelet theory'' IEEE Custom Integrated Circuit Conference(CICC) Sep. , 2003,San Jose,CA, U.S.A.pp.257-260.
Yeshwant Kolla, Y.Kim, John Carter, "A Novel 32-bit Scalable Multiplier Architecture'', Great Lake Symposium on VLSI, April 28-29, 2003,Washington D.C.,USA,pp.241-244.
B. Jin, Park, Y. Kim, Lombardi, "Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems'', IEEE International Symposium on Network Computing and Applications(NCA-03), April 16-18, 2003, Cambridge, Boston, MA, USA, pp.341-348.
Choi, Pottinger, and Y. Kim, "Need for Undergraduate and Graduate-Level Education in Testing of Microelectronic Circuits and Systems", IEEE 2003 International Conference on Microelectronic Systems Education, June 2003, Los Angeles, CA, U.S.A., pp.121-122.
K.M. George, N. Park, M. Choi, Y.B. Kim and F. Lombardi, "Environmental Based Characterization of SoC for Stratified Testing'', IEEE Instrumentation and Measurement Technology Conference,May 20-22, 2003, Vail, CO, U.S.A, pp.327-332.
M. Choi, N. Park, V. Piuri, Y.B. Kim and F. Lombardi, "Evaluating the Repair of System on Chip(SoC) Instrumentation Using Connectivity'', IEEE IMTC(Instrumentation and Measurement Technology Conference), May 20-22, 2003,Vail,CO, USA, pp.309-314.
F. Karimi, Y.B. Kim, F. Lombardi and N. Park, "Compression of Partially Specified Test Vectors in an ATE Environment'', IEEE IMTC(Instrumentation and Measurement Technology Conference), May 20-22, 2003,Vail,CO,USA, pp.999-1004.
N. Park, M. Choi, Y.Kim, "Soft Test/Repair of CCD-based Digital X-ray Instrumentation'', IEEE IMTC(Instrumentation and Measurement Technology Conference), May 20-22, 2003,Vail,CO,USA, pp.315-320.
Young Jun Lee and Y.Kim, "A Novel Clocking Strategy for Dynamic Circuits", IEEE International Symposium on Quality Electronic Design(ISQED) Conference March 16-20, 2003,San Jose U.S.A.pp.307-312.
M. Choi, N. Park, Y. Kim, Lombardi, "Hardware/Software Co-Reliability Design in Configurable MCM", 2002 Pacific Rim International Symposium on Dependable Computing (PRDC2002), Tsukuba, Japan, Dec. 16-18, 2002., pp.67-71.
Hashempour and Y.Kim, "A Test Vector Generation Methodology For Crosstalk Noise Faults", 2002 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT'02) Conference, Vancouver, Canada, November, 2002, pp.40-47.
M. Choi, N. Park, Y. Kim, Lombardi, "Balanced Redundancy Utilization for Dependable Embedded Memory System Core", 2002 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT'02) Conference, Vancouver, Canada, November, 2002, pp.419-427.
Dae Woon Kang and Y.Kim, "Design of Enhanced Differential Cascode Voltage Switch Logic(EDVSL) Circuits for High performance fan-In gate", IEEE International ASIC/SOC Conference 2002, pp.309-313.
Dae Woon Kang and Y. Kim, "Design Flow of Robust Routed Power Distribution for Low Power ASIC",'02 May. ISCAS,Phoenix,Arizona,U.S.A.,(Volume) I-181 ~ I-184.
Y. Kim, et al, "Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS", Advanced Research in VLSI Conference, pp 132-147, March 2001, Salt Lake City, Uath, U.S.A. pp.132-147.
Y. Kim, et al, "A Digital Trim-Controlled OP Amp. Compensation Technique", IEEE Midwest Symposium on Circuits and Systems 2001, August 2001,Fairborn,OH, USA, pp.211-214.
Y.Kim, et al, "A Digital Trim-Controlled On-Chip RC Oscillator", IEEE Midwest Symposium on Circuits and Systems 2001, August 2001, Fairborn, OH, USA, pp.882-885.
Dae-Woon Kang, Y. Kim, "A Deep Sub-Micron SRAM Cell Bistable Analysis Methodology", IEEE Midwest Symposium on Circuits and Systems 2001, August 2001, Fairborn, OH, USA, pp.858-861.
Shivakumar Sompur, Y.B. Kim, "An Investigation into Adiabatic Circuits", IEEE Midwest Symposium on Circuits and Systems 2001, August 2001, Fairborn, OH, USA, pp.294-297.
Woo-Jin Kim, Y. Kim, "A Localized Self Resetting Gate Design Methodology", IEEE Midwest Symposium on Circuits and Systems 2001, August 2001, Fairborn, OH, USA, pp.305-308.
Y.Kim, T. Chen, " CMOS Delay Locked Loop(DLL) for Reducing Clock Skew to Under 500pS", '97 Jan. Asia and South Pacific Design Automation Conference,Chiba, Japan(Special Feature Award/Full Custom Mixed Mode Circuit Design).
Y.Kim, T. Chen, "Clock Skew on DRAM/Logic Merged Technology Based Systems", '96 May. ISCAS,Atlanta,Georgia,USA, volume 4,pp.141-144.
Y.Kim, T. Chen, "Assessing Merged DRAM/Logic Technology",'96 May. ISCAS Atlanta, Georgia,USA, volume 4 pp.133-136.
Y.Kim, T. Chen, "On System Level Performance of DRAM/Logic Merged Technology", International Technical Conference on Circuits, Systems, Computers and Comminications, Seoul, Korea, pp.991-994, July 1996.
Y.Kim, T. Chen, "0.8mu$m CMOS Optical Clock Receiver Design", '95 Dec. International Conference on Microelectronics, Kuala Lumpur, Malaysia, pp.37-40.
Y.Kim, William N. Carr, "CMOS Sensor Interface for a Robotics LAN", '89 June. UGIM Conference, Amherst, Massachusetts,USA, pp.265-267.
Y.Kim, "CMOS PCM COMBO Integrated Circuit Design including Input Offset Compensation Technique for Comparator",'85 KIEE,Seoul,Korea.
Y.Kim, "VTR Color AFC Integrated Circuit Design",'83 KIEE Conference,Seoul, Korea.
Report
High Performance and Low Power ASIC Design Methodology
(Focusing on Design For Testability)