Education

Ph.D., Electrical and Computer Engineering, Colorado State University

M.S.E.E., Electrical and Computer Engineering, New Jersey Institute of Technology(NJIT)

B.S., Electronic Engineering, Sogang University, Seoul, South Korea

Research Interest

High Speed Digital/Analog Integrated Circuit Design

Clocking scheme for high performance VLSI systems including on-chip clock skew analysis and clock distribution

High speed integrated crcuit signal integrity and physical CAD tool development

Low power and high speed circuit design methodology and technology

Circuits Design Based on Nanoelectronics

High speed system integration for signal processing and communication applications

Innovative circuits and system application

Merged DRAM logic technology

Industrial Experiences

Researcher at Electronics and Telecommunications Research Institute(ETRI) : Involved in Communications Chip Design

Senior Design Engineer at Intel Corp., Hillsboro, OR : Involved in Intel Pentium-Pro CPU Design Project, Micro-controller Chip Design

Member of Technical Staff at Hewlett Packard Company, Fort Collins, CO : Involved in PA RISC 8000 CPU Chip Design Project

Individual Technical Contributor at Sun Microsystems Inc., Sunnyvale, CA: Involved in Ultra SparcV CPU Chip Design Project

Invited Speaker

VLSI Systems Design Based on Carbon Nano Tube Field Effect Transistor (CNTFET), Yonsei University, Seoul, South Korea, October 2016.

Low Power SoC Design Approach for Mixed-Mode Integrated Circuits Design, Chungbuk National University. Chungju, South Korea, July 2014.

A Leakage Minimization Techniques for Nano-Scale CMOS VLSI Circuits Design, Chungbuk National University, Chungju, South Korea, July 2013.

Nanotechnology Based Low Power Design and Latest Trend, Electronics and Telecom- munications Research Institute(ETRI), Seoul, South Korea, July 2013.

Power Saving Techniques for Nanoscale Integrated Circuits, Hanyang University, Seoul, Korea, July 2012.

Power Estimation and Saving Method for Mobile GPU, Samsung Advanced Institute of tEchnology, Kiheung, Korea, July 2012

A New Paradigm of Low Power VLSI Design Methodology, Chungbook National Uni- versity, Chungju, Korea, July 2012.

Low Power Digital Integrated Circuits Design Approach Based on Nanoscale Electronics, JoongAng University, Soul, Korea, July 2012.

Leakage Power Reduction Techniques in Modern Nanoscale VLSI Design, Xiamen Microelectronics Co. Xiamen, China, July 2011

A New Paradigm of VLSI Design Methods Based on Emerging Nano Technology, JoongAng University, Seoul South Korea, July 2011.

Leakage Reducing Circuit Design Techniques for Nanoscale CMOS Integrated Circuits, Pogang, Pohang University of Science and Technology, South Korea, July 2010.

Circuit Design Techniques for Carbon Nanotube FETS technology, Hanyang University, Seoul, South Korea, July 2010

Leakage Reducing Circuit Design Techniques for Nanoscale CMOS Integrated Circuits, Korea University, Seoul, South Korea, July 2010.

VLSI Design Technology Innovation for Ultra Low Power High performance in Nano Era, Samsung Advanced Institute of Technology, Kiheung, South Korea, July 2009.

VLSI Design Technology Innovation for Ultra Low Power High performance in Nano Era, Pohang University of Science and Technology, Pohang, South Korea, Jly 2009.

Keynote Speaker, The New Paradigm of the High Performance and Low Power Full Custom Design Method Based on Nanotechnology, Workshops on Unique Chips and Systems 2009(UCAS-5), Boston, MA, 2009.

A New Paradigm of the Low Poqwer High Performance VLSI design Based on Emerging Nano Technologies, Samsung Advanced Institute of Technology, Kiheung, Korea, July 2008.

A New Paradigm of the Low Poqwer High Performance VLSI design Based on Emerging Nano Technologies, Samsung Advanced Institute of Technology, Kiheung, Korea, July 2008.

A Novel Leakage Current Minimization Technique in Modern VLSI Design, Kyungwon University, Bundang, Korea, July 2008.

Adaptive Body Biasing Technique for Optimum Performance and Minimal Leakage Power for Nanoscale VLSI Systems, Inha University, Incheon, Korea, July 2007.

Full Custom Design Techniques Based on CMOS Nano Technology, Seloco Inc., Seoul, Korea, July 2007.

Design Technique to Reduce Leakage Current in CMOS Nano VLSI Chip, Samsung Advanced Institute of Technology, Kiheung, Korea, July 2007.

Phase Lock Loop(PLL) Design Considering Power Supply Noise and Leakage Current Basecd on Nano CMOS Technology, Yonsei University, Seoul, Korea, July 2007.

CMOS Power Aware Digital Core Logic Design Technique, Korean Advanced Institute of Science and Technology(KAIST) Daejon, Korea, July 2006.

Low Power Digital Adaptive Voltage Controller Design, Yonsei University, Seoul, Korea, July 2006.

CMOS Low Power Voltage Scaling System Design Using Finite State Machine, Inha University, Incheon, Korea, July 2006.

A CMOS Sub-1V power Supply Band-gap Reference Voltage Generator with an Extended Temperature and Voltage Range, Hanyang University, Ansan, Korea, July 2005.

Low Power Digital Adaptable Voltage Controller Based on Hybrid Control and and Reverse Phase Mode, National Semiconductor Company, Longmont CO, USA, August 2004.

Low Power Digital Adaptable Voltage Controller Based on Hybrid Control and and Reverse Phase Mode, Busan University, Busan, Korea, June 2003

Power Saving Techniques for TFT LCD Controller Chip Design, Samsung Electronics, June 2003

High Speed Full Custom VLSI Design Tutorial and Interconnect Related Clock/Power Issue, IC Design Education Center(IDEC), Seoul, South Korea, 2002

VLSI Circuit Design Reliabilty Tutorial, SeoDu InChip, Seoul, South Korea, 2002

Clock and Power Distribution for DRAM/Logic Merged VLSI Systems, Hewlett Packard Lab, Palo Alto, 1999

High Performance VLSI Circuit Design Methodology, Korean Advanced Institute of Science and Technology(KAIST), 1998 Samsung Advanced Institute of Technology, 1998

Power Supply IR Drop Analysis Methodology for High Performance, Johns Hopkins University, Baltimore, MD, 1998

Clock Signal Distribution for a High Performance Microprocessor, Colorado State University, Fort Collins, CO, 1997

VLSI Systems Design Using DRAM/Logic Merged Technology, Lucent Technology(Bell Lab Innovations), Murray Hill, New Jersey, 1997

High Performance VLSI Circuit Design Methodology, Samsung Advanced Institute of Technology, Kiheung, Korea, 1998

Closk Skew Analysis Methodology for GHz Level Microprocessor, Korean Advanced Institute of Science and Technology, Daejon, Korea, 1998

Deep Sub-Micron Design Methodolgy and Issues, San Jose State University, San Jose, California, 1997

DRAM/Logic Merged Design Technology and Its Applications, Samsung Electronics Comapany, Seoul Korea, 1996

Intel P6(Pentium Pro) Floating Point Execution Unit design, Samsung Electronics Company, Seoul, korea, 1994

Patents

Low Power Dual Power Supply High Resolution Comparator Design(U.S. PAT NO.5374859)

Signal Deskewing Using Programmable Dual Delay Locked Loop(U.S. PAT NO.5880612)

A Method to Use On-Chip Temperature Sensors For Detection Of Trojan Circuits (U.S. PAT NO.10074580)

Impedance Calibration Device for Semiconductor Device (U.S. PAT NO.9998123)

Receiver Circuitd for DRAM (South Korea Pat NO.1020180055308)