Publications 
Siva Kotipall, Yong-Bin Kim, and Minsu Choi, "Asynchronous AES (Advanced Encryption Standard) Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance",Journal of Electrical and Computer Engineering, Vol. 25, pp. 1-13(Article ID 837572), July 2014.
Inseok Jung, Yong-Bin Kim, and Kyung Ki Kim "Cost Effective Test Methodology Using PMU For Automated Test Equipment Systems",International Journal of VLSI design & Communication Systems (VLSICS), Vol.5, No.1, pp. 15-27, Feb. 2014.
Jing Lu, Jing Yang, Yong-Bin Kim, Joseph Ayers, and Kyung Ki Kim "Implementation of Excitatory CMOS Neuron Oscillator for Robot Motion Control Unit",JSTS(Journal of Semiconductor Technology and Science), Vol. 14, No.4, pp. 383-900, August 2014..
Jun Zhao,Yong-Bin Kim, and Kyung Ki Kim "A Charge Pump for Negative High Voltage Generation with Variable Voltage Gain",IEICE(The Institute of Electronics, Information and Communications Engineers) (Submitted).
Hari Chauhan, Yongsuk Choi, Marvin Onabajo, Inseok Jung,Yong-Bin Kim,"Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches",IEEE Transactions on VLSI Systems, vol. 22, no. 3, pp. 497 - 506, March 2014.
Jing Yang and Yong-Bin Kim,"Self Adaptive Body Biasing Scheme for Leakage Power Reduction under 32nm CMOS Regime",International Journal of Advanced Computer Science, Vol. 3, No. 9, pp. 453-459, Sep., 2013.
Rajashekhar Modugu, Yong-Bin Kim, and Minsu Choi,"A Fast Low-Power Modulo $2^{n}$ +1 Multiplier",IEICE(The Institute of Electronics, Information and Communications Engineers) Express(Submitted)
Hari Chauhan, Yongsuk Choi, Marvin Onabajo, Inseok Jung, and Yong-Bin Kim,"Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches",IEEE Transactions on VLSI Systems(Under revision).
Sheng Lin, Yong-Bin Kim, and F. Lombardi, "Design of Ternary Memory Cell Using CNTFETs",IEEE Transactions on Nanotechnology, Vol. 11, No.5, September 2012, pp.1019-1025.
Tina Marie Rookmmaker, Moon Seok Kim, and Yong-Bin Kim, "Design and Analysis of the Quadfferential Amplifier", Elsevier Microelectronics, Vol. 43, Issue 10, Oct 2012, pp. 697-707.
Sheng Lin, Yong-Bin Kim, and Fabrizio Lombardi, "Analysis and Design of nanoscale CMOS Storage Elements for Single Event Hardening with Multiple Node Upset", IEEE Transactions on Device and Materials Reliability, Vol 12, No. 1, March 2012, pp.68-77.
Heungjun Jeon and Yong-Bin Kim, "A Novel Low-Power, Low-Offset, and High-Speed CMOS Dynamic Latched Comparator ", Analog Integrated Circuits and Signal Processing, Vol. 70, No. 3, March 2012, pp.337-346.
Inseok Jung and Yong-Bin Kim, "A CMOS Low Power Digital Polar Modulator System Integration for WCDMA Transmitter", IEEE Transactions on Industrial Electronics, Vol. 59, No.2, Feb. 2012, pp. 1154-1160.
Kyung Ki Kim, Yong-Bin Kim, and Ken Choi, "Hybrid CMOS and CNFET Power Gating in Ultra-Low Power Voltage Design", IEEE Transactions on Nanotechnology, Vol.10, No. 6, Nov. 2011, pp.1439-1448.
Yong-Bin Kim, "Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor ", Transactions on Electrical and Electronic Materials, Vol. 12, No. 5, pp. 175-188, October, 2011.
Sheng Lin, Yong-Bin Kim, F. Lombardi, ", ``Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS ", IEEE Transactions on Very Large Scale Integration Systems, Vol.2, No.7, July 2011, pp.1315-1319.
Sheng Lin, Yong-Bin Kim, F. Lombardi, "A 11-Transistors Nanoscale CMOS Memory Cell for Hardening to Soft Errors", IEEE Transactions on VLSI Systems, Vol. 19, No. 5, May 2011, pp.900-904.
Sheng Lin, Yong-Bin Kim, and F. Lomabrdi, "The CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits&qaot;, IEEE Transactions on Nanotechnology,Vol. 10, Number 2, pp.217-225, March 2011.
Rajashekhar Modugu, Yong-Bin Kim, and Minsu Choi, "A Fast Low-Power Modulo 2n + 1 Multiplier", IET Computers and Digital Techniques(Submitted).
Geunho Cho, F. Lombradi, and Yong-Bin Kim, "Modeling Undeposited CNTs for CNTFET Operation", IEEE Transactions on Device and Materials Reliability, Vol.11, No.2, Jun 2011, pp.263-272.
Kyung Ki Kim, Yong-Bin Kim, and Ken Choi, "Hybrid CMOS and CNFET Power Gating in Ultra-Low Power Voltage Design", IEEE Transactions on Nanotechnology(Accepted).
Yong-Bin Kim,"Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics", Transactions on Electrical and Electronics Materials, Vol. 11, No. 3, June , 2010, pp. 93-105.
Sheng Lin, Yong-Bin Kim, and Fabrizio Lombardi, "The Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection", IEEE Transactions on Nanotechnology, Vol. 9, Issue 1, Jan. 2010, pp.30-37.
Sheng Lin, Yong-Bin Kim, F. Lombardi, "A Design and Analysis of a 32nm PVT Tolerant CMOS SRAM Cell for Low Leakage and High Stability", Elsevier Integration, the VLSI Journal, DOI 10.1016/j.vlsi.2010.01.003, Volume 43, No.2, Mar. 2010. pp.176-187.
Jun Zhao and Yong-Bin Kim, "A Low Power Digitally Controlled Oscillator For All Digital Phase Locked Loops", VLSI Journal, vol. 2010(2010), Jan. 2010, Article ID 946710, pp. 1-11, 2010. doi:10.1155/2010/946710.
HeungJun Jeon, Yong-Bin . Kim,and Minsu Choi, "Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems>'', IEEE Transactions on Instrumentation and Measurement, Vol. 59, No. 5, May 2010, pp.1127-1133.
Joseph Ayers, Nikolai Rulkov, Dan Knudsen, Yong-Bin Kim, Alexander Volkovskii, Allen Selverston, ", ``Controlling Underwater Robots with Electronic Nervous Systems", Special Issue on Biologically Inspired Robots, Applied Bionics and Biomechanics, Vol. 7, No. 1, March 2010, pp. 57-67.
Rajashekhar Modugu, Nohpill Park, Yong-Bin Kim, and Minsu Choi,"Fast Low Power Modulo 2**n + 1 Squarer Hardware for Efficient Data processing'', ACM Transactions on Computer Systems(ACM TOCS)(Submitted).
Sheng Lin, Yong-Bin Kim, F. Lombardi, "A 11-Transistors Nanoscale CMOS Memory Cell for Hardening to Soft Errors", IEEE Transactions on VLSI Systems(Accepted).
Kyung Ki Kim and Yong-Bin Kim,"Statistical Timing and Leakage Power Analysis of PD-SOI Digital Circuits,'', Analog Integrated Circuits and Signal Processing, vol. 60, No.2, Issue 1, 2009, pp. 127-136.
Rajashekhar Modugu, Nohpill Park, Yong-Bin Kim, and Minsu Choi,"A Fast Low Power Modulo 2**n + 1 Multiplier'', Elsevier Journal of System Architecture(Submitted).
Kyung Ki Kim and Yong-Bin Kim," Statistical Timing and Leakage Power Analysis of PD-SOI Digital Circuits,'', Analog Integrated Circuits and Signal Processing, vol. 60, No.2, Issue 1, 2009, pp. 127-136
Kyung Ki Kim and Yong-Bin Kim, "Design Methodology for Power Supply Noise and Leakage Current Control in Nanoscale CMOS VLSI Systems Design", IEEE Transactions on VLSI Systems, V0l. 17, No. 4, pp. 517-528, April 2009.
Cristiana Bolchini and Yong-Bin Kim, " "Editorial on defect and Fault Tolerance in VLSI Systems'' Journal of Electronic Testing: Theory and Applications, Vol. 25, No. 1-3, June 2009, pp.5-8.
Kyung Ki Kim, Y. Kim, Fabrizio Lombardi, "A Novel Statistical Timing and Leakage Power Characterization of Partially-Depleted Silicon-On-Insulator(SOI) Gates''', IEEE Transactions on Instrumentation and Measurement, Vol. 58, No. 2, pp. 401-410, February 2009.
Cristiana Bolchini and Yong-Bin Kim' " ,``Guest Editorial on Defect and Fault Tolerant VLSI Systems 2009 ", Journal of Electronic Testing: Theory and Application Special Issue on Defect and Fault tolerant VLSI 2008, vol. 25, Numbers 1-3, Jun, 2009, pp. 4-5.
Byunghyun Jang, Yong-Bin Kim, F. Lombardi, "Monomo Control For Error Tolerance In DNA Self-Assembly'' ,", Journal of Electronic Testing: Theory and Application, Vol. 24, Numbers 1-3, June, 2008, pp.271-284.
Kyung Ki Kim, Jing Hwang, Yong-Bin Kim, and F. Lombardi "Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels", IEEE Transactions on Industrial Informatics, Vol. 4, No. 2, May 2008, pp. 134-143.
Kyung Ki Kim and Yong-Bin Kim, "Standby Power Reduction Using Optimal Supply Voltage and Body-Bias Voltage'', IEICE Electronics Express(ELEX), Vol. 5, No. 15, pp. 556-561, August 2008.
Kyung Ki Kim and Yong-Bin Kim, "Phase Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology '', Journal of Semiconductor Technology and Science, Vol. 7, Number 4, December 2007, pp. 161-166.
Kyung Ki Kim and Yong-Bin Kim, "A 32nm and 0.9V CMOS Phased Locked loop with Leakage Current and Power Supply noise Compensation'', Journal of Semiconductor Technology and Science, Vol. 7, Number 1, March 2007, pp. 11-19.
Young Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin Kim, "A Low Power CMOS Electronic Central Pattern Generator Design for Biomimetic Underwater Robot'', Elsevier Neurocomputing Journal, Vol 71, Issue 1-3, December 2007, pp. 284-296.
Kyung Ki Kim, Yong-Bin Kim,"Ultra Low Voltage high Speed Schmitt Trigger Circuit in SOI MOSFET Technology'', IEICE Electronics Express(ELEX), Vol. 4 (2007) , No. 19 pp.606-611.
Kyung Ki Kim, Yong-Bin Kim, Mimsu Choi, Nohpill Park,""Leakage Minimization Technique For Nanoscale CMOS VLSI Based On Macro-Cell Modeling'', IEEE Design and Test of Computers, July-August, 2007, pp322-330.
Kyung Ki Kim, Yong-Bin Kim, F. Lombardi, "Power Supply Network Aware Timing Analysis Using S-Parameter in Nanometer Digital Circuits,", IEEE Design and Test of Computers(submitted).
Rui Tang, Fengming Zhang, Yong-Bin Kim, "Design Metal-Dot Based QCA Circuits Using SPICE Model", Elsevier Microelectronics Journal, Vol. 37/8, Jun. 2006, pp 821-827.
Dae Woon Kang, Y. Kim, James Doyle, "A High Performance Fully Digital Synchronous Buck Converter Power Delivery System Based on Finite State Machine'', IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 14, No 3, pp.229-240, March 2006.
Young Bok Kim, Y. Kim, J. Doyle, "A CMOS Low Power Digital Polar Modulator Design for WCDMA Transmitter'', IEEE Transactions on Circuits and Systems(Under Review).
Jihyun Lee and Y.Kim, "ASLIC: A Low Power CMOS Analog Circuit Design Automation``, Elsevier Integration, the VLSI Journal, vol. 39, No. 3, June 2006, pp. 157--181.
Fengming Zhang and Y. Kim, "SET-Based Nano-Circuit Simulation and Design Method Using HSPICE'', Elsevier Microelectronics Journal, Vol 36/8 pp. 741-748.
Marco Ottavi, L. Schiano, X. Wang, Y. Kim, F. Lombardi, "Evaluating the Yield of Repairable SRAM for ATE'', IEEE Transactions on Instrumentation and Measurement, Vol. 55, No. 5, October 2006, pp.1704-1712.
Shivakumar Sompur and Y.Kim, "An Investigation into Adiabatic Circuits for Deep Sub-Micron VLSI Application", Elsevier Integration, The VLSI Journal(In Press, will appear soon).
L. Schiano, Young Jun Lee, T. Kane, Y-B Kim, "Measuring the Timing Jitter of ATE in the Frequency Domain'', IEEE Transactions on Instrumentation and Measurement, Vol. 55, No. 1, pp280-289, 2006.
Marco Ottavi, L. Schiano, X. Wang, Y. Kim, F. Lombardi, "Yield Estimation Method of SRAM Array'', IEEE Transactions on Instrumentation and Measurement, Oct., 2006.
N. Park, K.M,George, M. Choi, Y. Kim, "Environmental-based Characterization of SoC-based Instrumentation Systems for Stratified Testing'', IEEE Transactions on Instrumentation and Measurement, vol.54, No.3, Jun. 2005, pp1241-1248.
Fengming Zhang and Y. Kim, "SET-Based Nano-Circuit Simulation and Design Method Using HSPICE'',Elsevier Microelectronics Journal, Vol 36/8, MAr. 2005, pp. 741-748.
James T. Doyle, Young Jun Lee, Y.Kim, "A CMOS Subbandgap Reference Voltage Circuit with 1V Supply Voltage'', IEEE Transactions on Solid State Circuits, January, 2004. pp.252-255.
M. Choi, N. Park, V. Piuri, Y. Kim, "Balancing the Redundancy in Embedded Memory Cores for Dependable Systems'', Elsevier Journal of System Architecture-DFT, Special Issue: Design and Test of System on a Chip, Vol. 50, No. 5, pp.281-285, April 2004.
James T. Doyle, Young Jun Lee, Y.Kim, "Improved DAC Modeling Techniques Based on Wavelet Theory'', Elsevier Microelectronics Journal, Vol. 35, Issue5, May 2004, pp.451-460.
Woo Jin Kim and Y. Kim, "Automating the Design Approach to Wave Pipelined Circuits'' IEEE Design and Test of Computers'', Nov/Dec 2003, pp.51-58.
Soha Hassoun, Y. Kim, and F. Lombardi, "Introduction: Clockless Digital VLSI Circuit'' IEEE Design and Test of Computers'', Nov/Dec 2003, pp.5-8.
B. Jin, K.M. George, N. Park, M. Choi, Y.B. Kim, "Modeling and Analysis of Soft-Test/Repair for CCD-based Digital X-Ray Systems'', IEEE Transactions on Instrumentation and Measurement, Vol.52, No.6, Dec. 2003, pp.1713-1721
Young Jun Lee, Fabrizio Lombardi, Y.Kim, "Analysis and Measurement of Timing Jitter Induced by Radiated EMI Noise in Automatic Test Equipment'', IEEE Transactions on Instrumentation and Measurement, Volume 52, Number6 December 2003, pp.1749-1755
Shivakumar Sompur and Y.Kim, "An Investigation into Adiabatic Circuits for Deep Sub-Micron VLSI Application", Elsevier The VLSI Journal.
Y.Kim, T. Chen, "Assessing Merged DRAM/Logic Merged Technology", Elsevier Integration, the VLSI Journal, pp.179-194, September 1999.