People 

Professor

  • Yong-Bin Kim

    Department of Electrical
    and Computer Engineering

    327 Dana Research Center
    Phone: (617) 373-2919
    Fax: (617) 373-8970
    E-mail : ybk@ece.neu.edu

    (Complete CV PDF)

  • Education
  • Ph.D., Electrical and Computer Engineering, Colorado State University
  • M.S.E.E., Electrical and Computer Engineering, New Jersey Institute of Technology(NJIT)
  • B.S., Electronic Engineering, Sogang University, Seoul, South Korea
  • Research Interest
  • High Speed Digital/Analog Integrated Circuit Design
  • Clocking scheme for high performance VLSI systems including on-chip clock skew analysis and clock distribution
  • High speed integrated crcuit signal integrity and physical CAD tool development
  • Low power and high speed circuit design methodology and technology
  • Deep sub-micron device phenomena
  • High speed system integration for signal processing and communication applications
  • Innovative circuits and system application
  • Merged DRAM logic technology
  • Industrial Experiences
  • Researcher at Electronics and Telecommunications Research Institute(ETRI) : Involved in Communications Chip Design
  • Senior Design Engineer at Intel Corp., Hillsboro, OR : Involved in Intel Pentium-Pro CPU Design Project, Micro-controller Chip Design
  • Member of Technical Staff at Hewlett Packard Company, Fort Collins, CO : Involved in PA RISC 8000 CPU Chip Design Project
  • Individual Technical Contributor at Sun Microsystems Inc., Sunnyvale, CA: Involved in Ultra SparcV CPU Chip Design Project
  • Invited Speaker
  • A New Paradigm of the Low Poqwer High Performance VLSI design Based on Emerging Nano Technologies, Samsung Advanced Institute of Technology, Kiheung, Korea, July 2008.
  • A Novel Leakage Current Minimization Technique in Modern VLSI Design, Kyungwon University, Bundang, Korea, July 2008.
  • Adaptive Body Biasing Technique for Optimum Performance and Minimal Leakage Power for Nanoscale VLSI Systems, Inha University, Incheon, Korea, July 2007.
  • Full Custom Design Techniques Based on CMOS Nano Technology, Seloco Inc., Seoul, Korea, July 2007.
  • Design Technique to Reduce Leakage Current in CMOS Nano VLSI Chip, Samsung Advanced Institute of Technology, Kiheung, Korea, July 2007.
  • Phase Lock Loop(PLL) Design Considering Power Supply Noise and Leakage Current Basecd on Nano CMOS Technology, Yonsei University, Seoul, Korea, July 2007.
  • CMOS Power Aware Digital Core Logic Design Technique, Korean Advanced Institute of Science and Technology(KAIST) Daejon, Korea, July 2006.
  • Low Power Digital Adaptive Voltage Controller Design, Yonsei University, Seoul, Korea, July 2006.
  • CMOS Low Power Voltage Scaling System Design Using Finite State Machine, Inha University, Incheon, Korea, July 2006.
  • A CMOS Sub-1V power Supply Band-gap Reference Voltage Generator with an Extended Temperature and Voltage Range, Hanyang University, Ansan, Korea, July 2005.
  • Low Power Digital Adaptable Voltage Controller Based on Hybrid Control and and Reverse Phase Mode, National Semiconductor Company, Longmont CO, USA, August 2004.
  • Low Power Digital Adaptable Voltage Controller Based on Hybrid Control and and Reverse Phase Mode, Busan University, Busan, Korea, June 2003
  • Power Saving Techniques for TFT LCD Controller Chip Design, Samsung Electronics, June 2003
  • High Speed Full Custom VLSI Design Tutorial and Interconnect Related Clock/Power Issue, IC Design Education Center(IDEC), Seoul, South Korea, 2002
  • VLSI Circuit Design Reliabilty Tutorial, SeoDu InChip, Seoul, South Korea, 2002
  • Clock and Power Distribution for DRAM/Logic Merged VLSI Systems, Hewlett Packard Lab, Palo Alto, 1999
  • High Performance VLSI Circuit Design Methodology, Korean Advanced Institute of Science and Technology(KAIST), 1998 Samsung Advanced Institute of Technology, 1998
  • Power Supply IR Drop Analysis Methodology for High Performance, Johns Hopkins University, Baltimore, MD, 1998
  • Clock Signal Distribution for a High Performance Microprocessor, Colorado State University, Fort Collins, CO, 1997
  • VLSI Systems Design Using DRAM/Logic Merged Technology, Lucent Technology(Bell Lab Innovations), Murray Hill, New Jersey, 1997
  • High Performance VLSI Circuit Design Methodology, Samsung Advanced Institute of Technology, Kiheung, Korea, 1998
  • Closk Skew Analysis Methodology for GHz Level Microprocessor, Korean Advanced Institute of Science and Technology, Daejon, Korea, 1998
  • Deep Sub-Micron Design Methodolgy and Issues, San Jose State University, San Jose, California, 1997
  • DRAM/Logic Merged Design Technology and Its Applications, Samsung Electronics Comapany, Seoul Korea, 1996
  • Intel P6(Pentium Pro) Floating Point Execution Unit design, Samsung Electronics Company, Seoul, korea, 1994
  • Patents
  • Low Power Dual Power Supply High Resolution Comparator Design(U.S. PAT NO.5374859)
  • Signal Deskewing Using Programmable Dual Delay Locked Loop(U.S. PAT NO.5880612)
  • Student

    Ph.D. Candidates
  • Inseok Jung
  • homepage: http://www.ece.neu.edu/~ijung/
  • E-mail : ijung@ece.neu.edu
  • Ho Joon Lee
  • homepage: http://www.ece.neu.edu/~hjlee/
  • E-mail : hjlee@ece.neu.edu
  • Nalin Silva
  • homepage: http://www.ece.neu.edu/~nsilva/
  • E-mail : nsilva@ece.neu.edu
  • Jung Yang
  • homepage: http://www.ece.neu.edu/~jyang/
  • E-mail : jyang@ece.neu.edu
  • Heung Jun Jeon
  • homepage: http://www.ece.neu.edu/~hjeon/
  • E-mail : hjeon@ece.neu.edu
  • YongSeok Choi
  • homepage: http://www.ece.neu.edu/~xliu/
  • E-mail : ychoi@ece.neu.edu
  • Jing Lu
  • homepage: http://www.ece.neu.edu/~jhu/
  • E-mail : jhu@ece.neu.edu
  • Master Students
  • Jiaping Gong
  • homepage: http://www.ece.neu.edu/~jgong/
  • E-mail : jgong@ece.neu.edu
  • Ogun Turkyilmaz
  • homepage: http://www.ece.neu.edu/~oturkyilmaz/
  • E-mail : oturkyilmaz@ece.neu.edu
  • Soumya Shi Begur
  • homepage: http://www.ece.neu.edu/~sbegur/
  • E-mail : sbegur@ece.neu.edu
  • Erica Hau
  • homepage: http://www.ece.neu.edu/~lhau/
  • E-mail : lhau@ece.neu.edu
  • Shakthi
    Muthuswamy
  • homepage:http://www.ece.neu.edu/~mmuthusw/
  • E-mail : mmuthusw@ece.neu.edu
  • Alumi (Gone but not forgotten)

    Ph.D. Degree
  • Woo Jin Kim
    (at AMD)
  • E-mail : woo.kim@amd.com
  • Dae Woon Kang
    (at Intel)
  • E-mail : Dae.Woon.Kang@intel.com
  • Young Jun Lee
    (at Nextchip Corp.)
  • E-mail : yjlee@nextchip.com
  • Yeshwant Kolla
    (at Qualcomm)
  • E-mail : Yeshwant.kolla@sun.com
  • J.C. Sousa
    (at Hewlett-Packard)
  • E-mail : jsousa@hp.com
  • Shivakumar Sompur
    (at Intel )
  • E-mail : shivakumar.sompur@intel.com
  • Fengming Zhang
    (at Oracle Corporation)
  • E-mail : fengming.zhang@oracle.com
  • Rui Tang
    (at Oracle corporation)
  • E-mail : rui.tang@oracle.com
  • Kyung Ki Kim
    (at Daegu University)
  • E-mail : kkkim@daegu.ac.kr
  • Young Bok Kim
    ()
  • E-mail :
  • Jun Zhao
    (at Marvell Technology)
  • E-mail : junzhao@marvell.com
  • Sheng Lin
    (at Broadcom Company)
  • E-mail : sheng.lin@broadcom.com
  • Master Degree
  • Duong Tran
  • /
  • Lan Zhang
  • /
  • Jae Young Heo
  • /
  • Ki Young Kwon
  • /
  • Jong Jin Lim
  • /
  • Jihyun Lee
  • /
  • Sathees Easwaramuthali
  • /
  • KwonJae Shin
  • /
  • Piotr Olejarez
  • /
  • Yao Ting Yeh
  • /
  • Ping Liu
  • /
  • Mari Shakthi
  • /
  • Yeshwant Kolla
  • /
  • Ed Collins
  • /
  • Tina Rookmaaker
  • /
  • Dipen Patel
  • /