PacMan Simulator - An Automantic Synthesized Simulator for Cycle-Accurate Multiprocessor Simulation

PacMan is a multiprocessor cycle-accurate simulator which can simulate a cluster of PEs connected by custom on-chip communication architectures, such as wormhole based packet-switching, fully connected crossbar switches or regular standalone buses. The topologies supported include mesh, torus and star shape.

The concurrency model used by PacMan is based on works by Wei Qin, who developed a fast ARM simulator SimIt-ARM.

Both the PE model (previously developed by Wei Qin) and On-Chip Communication Architecture (OCA) model are developed using the Operation State Machine (OSM). We provide a unique methodology where both the PE and OCA are modeled with the same style, thus enhancing simulation efficiecy and posing huge potential for further efforts such as model validation, verification, etc.

Strictly speaking, the software toolsuite we provide is an automatic simulation platform generator. The simulators themselves are synthesized from a hierarchy of machine specification languages. The goal is to provide the designers maximum flexibility in specifying the characteristics of the mult-PE based SoC, such as interconnection topology, the type of the network flow control, buffering scheme, etc. We provide a full toolsuite which can interpret the specification and synthesize the intended system simulator. Through simulation, critical system performance metrics such as timing, communication patterns are obtained. This "synthesis+simulation" approach enables the designers to have a trustworthy evaluation of the full system design in a relative short design cycle.

The minimum requirement for installing the software are a Redhat 7.0 box on X86 with Perl and current g++ compiler suites.

The software in in public domain and feedbacks are most welcomed.

Key Features and Highlights

  1. A C/C++ written cycle-accurate communication architecture simulator.
  2. A machine specification language hierarchy targeting at simulator synthesis.
  3. A library of reusable communication modules such as buffers (channel), arbiters and crossbars.
  4. A variety of selections of applicable communication network topology, e.g. bus, k-ary n-cube, torus, mesh, etc.
  5. Fully integrated with an accurate ARM PE model. Can simulate message passing based application binaries compiled by crosscompilers.
  6. Fast Simulation Speed. (> 7K cycles per second for a 16PE cluster with 7.2 flit per cycle traffic model)
  7. Fast design turn-around time. The entire process of synthesizing a simulator, running the simulation, takes less than 7 minutes.

Download

Download release 0.4 .

View README .

 

Reference

X.Zhu, W.Qin, S.Malik, Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation , Proceedings of International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), Sep, 2004( pdf , powerpoint )

X.Zhu, S.Malik, "Using A Communication Architecture Specification in an Application-driven Retargetable Prototyping Platform for Distributed Processing", Proceedings of 2004 Design Automation and Test in Europe Conference (DATE 04), Feb, 2004 (PDF )

W. Qin, S. Malik. Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation, Proceedings of 2003 Design Automation and Test in Europe Conference (DATE 03), Mar, 2003, pp.556-561. (PDF)

W. Qin, Mescal Architecture Description Language 1.0, Draft, Link

Last updated: April 16th, 2004