CoreConnect Bus Simulator - An Automantic Synthesized Simulator for Cycle-Accurate IBM CoreConnect Bus Model



Here we provide a complete model tookit which can model and simulate 32-bit IBM CoreConnect Bus Architecture using Operation State Machine (OSM) models.

The concurrency model - the OSM - is based on works by Wei Qin, who developed a fast ARM simulator SimIt-ARM.

The specification we used in this study is based on
1. IBM 32-bit Processor Local Bus Architecture Specification Version 2.9. pdf
2. PLB Functional Model Toolkit, Chap 6, PLB Bus Functional Language pdf

The Official IBM CoreConnect Website

The software in in public domain and feedbacks are most welcomed.

Key Features and Highlights

  1. A C/C++ written cycle-accurate coreconnect bus model and its corresponding description.
  2. A library of reusable communication modules such as timers, arbiters, etc.
  3. Fast Simulation Speed. (> 200K cycles per second for a 4 node bus architecture on a P4 with Linux )

Download

Download release 0.1 .

View README .

 

Reference

X.Zhu, W. Qin, S. Malik, Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation , Proceedings of International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), Sep, 2004( pdf , powerpoint )

X.Zhu, S.Malik, "Using A Communication Architecture Specification in an Application-driven Retargetable Prototyping Platform for Distributed Processing", Proceedings of 2004 Design Automation and Test in Europe Conference (DATE 04), Feb, 2004 (PDF )

W. Qin, S. Malik. Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation, Proceedings of 2003 Design Automation and Test in Europe Conference (DATE 03), Mar, 2003, pp.556-561. (PDF)

W. Qin, Mescal Architecture Description Language 1.0, Draft, Link

Last updated: Sep 11th, 2004