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Embedded Software Development in a System Level Design Context

System level design is one approach to tackle the complexity of designing a modern System-on-Chip. One major aspect is the capability of developing the system model without a special attention to the later occurring hardware software split. Both hardware and software can be developed seamlessly at the same time. It therefore allows a better integration between those traditionally separated development flows.
Simulated Bandwidth of models at different levels of abstraction.
Hardware / software co-simulation is needed for an efficient integrated HW/SW development. Depending on the design phase this co-simulation can be done at different levels of abstraction. They range from the very abstract simulation at the specification level down to the cycle accurate simulation of hardware and the software execution on an instruction set simulator.

The goals of this project address two separate aspects. For one, we want to abstractly model software the software execution environment. In addition, we want to automatically create all embedded software out of an abstract system model.

For the modeling part, we create abstract processor models at varying level of abstraction. We seek to identify essential features for processor modeling that yield sufficiently timing accurate results in an acceptable simulation time. Due to the wide popularity of the ARM processors (and our availability of the AMBA AHB bus models), we have chosen an instruction set simulator (SWARM) for the ARM7TDMI. We integrated the ISS into the System-on-Chip Design Environment (SCE), which allows us to quickly generate cycle accurate models of custom SoC architectures. We have integrated a real-time operating system (MicroC/OS-II by Micrium) to run on top of the ISS. This gives us the ability to explore the real-time implications of the software hardware interaction.

We have also developed a tool that automatically generates - based on the abstract model in the SLDL - the embedded software and targets the code to a chosen RTOS. This generation includes, code generation (generating software code inside each task), communication synthesis (creating drivers for internal and external communication), multi-task synthesis (targeting toward an existing RTOS, or converting to state-machine interrupt-based multi-tasking), and finally the binary creation that compiles and links everything together into a the final execution binary.

Relevant publications for the modeling aspect:
Relevant publications for the synthesis aspect:
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Result Oriented Modeling

Despite our optimistic title of the previous project "FAT: Fast and Accurate TLM", we analyzed TLMs for many different bus systems and quantified the TLM trade-off between speed and accuracy. A model is either fast or accurate for the general case (although there are cases where a TLM is accurate enough).

Now, we introduced ROM: Result Oriented Modeling, ROM principle, optimistic prediction, check for disturbing influence and prediction update.a modeling technique communication TLMs. ROM can eliminate the inaccuracies for TLM in many cases, yet it is able to retain the TLM speed advantage. ROM makes the assumption that an application only needs to observe the timing at a transaction boundary. On the other hand, everything inside the transaction is hidden.

With this assumption, ROM can rearrange or omit internal states to gain speed. Instead of simulating each bus cycle, ROM makes and optimistic prediction right at the beginning of the transaction. It uses calculates the transaction duration (Answering: How long will this transaction take, if there is no further preemption?). Then, at the end of the predicted time, it checks weather the assumptions did hold true. It updates the prediction, in case there was an unexpected preemption. With that ROM reaches both: speed and accuracy.

Relevant publications:

Fast and Accurate Transaction-Level Modeling

The field of embedded systems increasingly extends to more complex scenarios including safety critical systems. Distributed embedded real-time systems with many processors become necessary. Accurate communication modeling is an important issue for the design of those complex systems. However, efficient system level design requires also high execution performance especially for communication models.
Simulated Bandwidth of models at different levels of abstraction.
Recent research work introduced Transaction Level Modeling as a means of increasing the simulation performance. Here, large speed-up is gained by abstracting away communication details. Inevitably this results in a loss of simulation accuracy. However, due to the complexity of accuracy measurements and its statistical analysis, no clear expressive quantification of the speed-accuracy tradeoff prevails.

The goals of this research project include:
Relevant publications: top