HARDWARE DESIGN lANGUAGE ENVIRONMENT FOR QCA (HDLQ)

Emerging technologies have attracted a substantial interest in overcoming the physical limitations of CMOS as projected at the end of the Technology Roadmap; among these technologies, quantum dot cellular automata (QCA) relies on different and novel paradigms to implement dense, low power circuits and systems for high-performance computing. As applicable to existing technologies, a hierarchical process can be utilized to facilitate the design of QCA circuits. Tools and methodologies both at system and physical levels are required to support all design phases. This research proposes an HDL model to describe QCA “devices” (also referred elsewhere in the technical literature as building blocks, i.e., majority voter, inverter, wire, crossover) and facilitate the evaluation of their design. This tool, referred to as HDLQ, allows a designer to verify the logic characteristics of a QCA system, while supporting within a design environment different operational mechanisms (such as fault injection) and the unique features of QCA (such as bidirectionality and timing/clocking partitioning). The applicability of this design environment to various memory circuits for logic and timing verification is presented in detail. Various defective conditions for kinks due to thermodynamic effects and permanent faults due to manufacturing defects are considered for injection. The verilog library is available for research use here .

DESIGN OF CIRCUITS FOR QUANTUM-DOT CELLULAR AUTOMATA

Design of Memories in QCA 

In the past few decades, the exponential scaling in feature size and increase in processing power have been successfully achieved by VLSI using mainly CMOS technology; however there is substantial evidence  that emerging technologies (mostly based at nano scale ranges) will be required to supersede the fundamental physical limits of CMOS devices. Among these new technologies, Quantum-dot Cellular Automata (QCA) (first introduced at the University of Notre Dame) gives a solution at nano scale and also offers a new method of communication and information transformation.

A QCA cell can be viewed as a set of four charge containers or “dots”, positioned at the corners of a square. The cell contains two extra mobile electrons which can quantum mechanically tunnel between dots, but not cells. The electrons are forced to the antipodal corner positions by Coulomb repulsion.
In the computational model, the solution of the Hamiltonian associated with a QCA cell provides eigenstates which allow to derive the charge density on the system of four quantum dots. It is useful to define a quantity for the charge density of a given solution. This alignment could be either along the line through dot sites 1 and 3, or along the line through sites 2 and 4, as shown in Figure 1. 

Figure 1. QCA cell

Note that an isolated cell with all equal on-site energies would not present any preferred polarization; instead, perturbations due to charges in neighboring cells result in a strongly polarized ground state. Therefore, electrons have a preferred alignment along one of the two perpendicular cell axes, as shown. The polarization P measures the extent of this alignment. If the two extra electrons are completely localized on dots 1 and 3, the polarization is + 1 (binary 1); if they are localized on dots 2 and 4, the polarization is - 1 (binary 0). The tunneling between dots is controlled by periodically raising and lowering the energy of the tunneling barrier; this mechanism represents the clocking in QCA and is implemented by dividing the circuit layout in different zones and by giving to each zone the sequence of four phases. The four clock phases are called "switch", "hold" , "release" and "relax": during the switch phase the tunneling barrier is gradually raised eventually forcing the electrons into one of the two stable polarizations according to external Coulombic interactions; in the hold phase the tunneling barrier between the quantum dots is high and no tunneling takes place latching the polarization of the cell, during the release phase the tunneling barriers are lowered and finally in the relax phase the electrons are not localized on the dots. Unlike conventional logic circuits in which information is transferred by electrical current, QCA operates by the Coulombic interaction that connects the state of one cell to the state of its neighbors. The configuration of the polarization of a set of cells reflects the lowest energy state (ground state). For QCA, this results in a technology in which information transfer (interconnection) is the same as information transformation (logic manipulation) with low power dissipation.

 
Based on the cell layout, QCA can then be characterized at logic level. One of the basic logic gates in QCA is the so-called majority voter (MV) with logic function Maj(A,B,C) = AB + AC + BC. MV can be realized by 5 QCA cells, as shown in Figure 2 (b). Logic AND and OR functions can be implemented from the MV by setting an input (the so-called programming or control input) permanently to a “0” or “1” value. The inverter (INV) is the other basic gate in QCA and is shown in Figure 2(a). The binary wire and inverter chain (as interconnect fabric) are shown in Figure 2(c)(d).

Figure 2. Basic QCA devices 

A straightforward approach to implement a memory by QCA is to maintain a cell (zone) in the Hold phase as long as its value must be retained for storage. The main problem with this rather obvious approach is the requirement of an explicit control of the CMOS clock signal from the decoder (which is implemented in QCA). Also, the transfer of signals from QCA to CMOS requires a complicated sensing process using sophisticated electrometers. For a truly QCA based implementation, memory must be kept in motion, i.e the memory state has to be continuously moved through a set of QCA cells connected in a loop partitioned into 4 clocking zones and at any given time, one of them is in the Hold phase to retain the information. In the technical literature, QCA based memories can be mainly classified into parallel and serial architectures. A parallel architecture offers the advantage of low latency, at each memory cell, only one data bit is stored, so there is no delay in that bit reaching the Read/Write circuitry.
In a serial design, multiple bits are stored in each memory cell and share the Read/Write circuitry, thus resulting in
a delay proportional to the word size. The SQUARES [1] formalism has made an early attempt to design a serial QCA memory. The basic principle of this technique is to define a set of equally sized blocks, each performing a basic function in QCA. These blocks can then be tiled together to design more complex QCA circuits. The obvious advantage of this technique is the ease in the geometric layout; However, as the blocks are of standard size, a substantial unutilized area appears in each block, thus causing spatial redundancy and lower density in the overall design. Clocking each SQUARE requires a large number of clocking zones even for a modest memory size, thus also requiring a considerable amount of CMOS circuitry to generate the clocking signals. A high density architecture with  uniform access time has been introduced with the H-Memory architecture [2]. The H-Memory has a complete binary tree structure with control circuitry at each node; as the memory spirals are at the leaf nodes, an integration of logic and memory is accomplished in the layout, but the control circuitry and memory are logically separate (similarly to CMOS design). However unlike conventional designs, control and data bits are serialized. The bit stream enters the memory structure at the root node and traverses down the tree by utilizing one control bit for routing at every node in the path. The architectural choice of dealing with serial bit streams results also in rather complex control logic for QCA. The memory cell at each leaf node is a spiral allowing storage of several bits, while sharing clocking zones between multiple loops. In this design, the memory size at each spiral and the cell count do not have a linear relationship; each outer loop has an increasing diameter, thus requiring more QCA cells for its implementation (although its storage capacity remains constant). A conventional parallel memory architecture such as encountered in CMOS-based RAM design for QCA has also been proposed [3], this memory stores one bit at each memory cell. The single-bit memory cells allow the design of a simple Read/Write circuitry. 

The focus of the research activity is to explore possible different designs for QCA memories based in order to  improve over the previously proposed architectures different figures of merit. Two main approaches are investigated: the hybrid memory and the line based memory.

The hybrid memory architecture can be considered as an evolution of the serial memory. It is referred to as “hybrid” because it has serial write and parallel read capabilities. This characteristic permits to combine the low latency advantage of a parallel architecture with the low area requirement (and therefore high density) of a serial architecture. As a serial memory still incurs in slow access for both the write and read operations, this architecture uses a parallel read approach [4].

The line based memory is based on a novel logic arrangement for the MV, namely the signal wires to an MV can behave differently (either as input or output) in time depending on the clock phase in which they operate. This arrangement combined with a new clocking strategy, overcomes the limitation of a traditional unidirectional flow of logic signals in QCA. Differently from all previous architectures (based on a loop structure), the line based approach exploits the Majority Voter gate as a memory element that stores the value of a bit and propagates it as in a shift register. By suitably modifying the clock signal the execution of the four different phases of the cells (Hold, Switch, Release, Relax) can be controlled. The design relies on the bi-directional nature of QCA devices. Work has been done to investigate Serial [5] and Parallel [6] memories arrangements based on this new techniques.

 Relevant publications :

  1. D. Berzon and T. Fountain. A memory design in qcas using the squares formalism. In Proceedings Ninth Great Lakes Symposium on VLSI, pages 168–172, 1999.
  2. S. Frost, A. Rodrigues, A. Janiszewski, R. Rausch, and P. Kogge. Memory in motion: A study of storage structures in qca. In First Workshop on Non-Silicon Computing, 2002.
  3. K. Walus, A. Vetteth, G. Jullien, and V. Dimitrov. Ram design using quantum-dot cellular automata. In Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, volume 2, pages 160–163, 2003.
  4. M. Ottavi, S. Pontarelli, V. Vankamamidi, A. Salsano, F. Lombardi “Design of a QCA Memory with Parallel Read/Serial Write” in Proceedings of 2005 IEEE Computer Society Annual Symposium on VLSI Tampa, Florida, pp. 292-294, May 2005
  5. V. Vankamamidi, M. Ottavi, F. Lombardi “Tile Based Design of a Serial Memory in QCA” in Proceedings of ACM Great Lakes Symposium on VLSI Chicago, Illinois, pp. 201-206, Apr. 2005.
  6. V. Vankamamidi, M. Ottavi, F. Lombardi. “A Line-Based Parallel Memory for QCA Implementation” in IEEE Transactions on Nanotechnology, vol. 4, n 6, pp: 690 – 698, November 2005

FAULT TOLERANT DESIGN TECHNIQUES

The Solid State Mass Memory Project - University of Rome  "Tor Vergata"

The design of electronic systems for space applications must consider several problems related to the harsh environment in which the system is employed. As a matter of fact, in the space environment electronic components are stressed by a large number of physical phenomena, such as mechanical stresses, ionizing radiations and critical thermal conditions. To cope with these tight application specifics, the typical approach adopted is the development of space qualified electronic devices based on special and expensive technology processes. However the use of specific components implies some important drawbacks such as high costs and poor performances if compared to the Commercial Off The Shelf (COTS) components.

Therefore the development of reliable electronic systems by using COTS components could  provide several advantages. The goal of matching the reliability requirements is achieved by applying suitable system level methodologies as redundancy and coding. A typical application, where this approach can be very useful, is the design of space-borne mass memories. In fact, the rapid growth in capacity of semiconductor memory devices permits today the development of solid-state mass memories, which are competitive with tape recorders due to higher reliability, comparable density and better performances. Solid-state mass memories have no moving parts and their operational flexibility has made them suitable for many applications. To obtain memories with low latency time high throughput and storage capabilities, space qualified components are not a valid option, therefore the choice of COTS appears very appealing.

The SSMM connects the memory modules to the instruments using a crossbar matrix that connects the elements of the network. This solution is convenient with respect to a common bus in terms of bandwidth, latency and reconfiguration capability. In fact, the failure of a connection would not compromise the entire connection of the network but only the access to a specific node. Moreover, to improve both the fault tolerance and the memory usage, the SSMM implements a distributed file system on . Most of the functions performed by the file system are hardware based and handled locally on each memory module.

 

The top level of the SSMM can be seen as a black box connected by some links, used for carrying command signals and data. Although different types of links can be used to communicate with the SSMM, the SpaceWire (IEEE 1355 DS-DE) protocol is widely used in this application. SpaceWire is planned to become a European Space Agency (ESA) standard for on-board data-handling in the near future and is expected to be extensively adopted in future European missions. Each SpaceWire link can carry data at around 100 Mbit/sec, over distances of up to 10m. SpaceWire is intended to support the ready reuse of equipment developed for space applications. Moreover, the SSMM can be connected with a MIL 1553 bus, normally used in satellite platforms

The SSMM architecture can be split in two main units:

  1. The System Control Unit (SCU) manages the memory resources and provides system level reconfiguration

  2. The Memory Kernel Unit (MKU) manages the bi-directional data flow between users and memory chips;

The desired reliability of the SSMM system is achieved both by means of architectural redundancies, and by introducing Error-Correcting Codes (ECC), granting data integrity
 

The related research activity performed during the design of the SSMM can be summarized in the following phases which refer also to the relevant publications:

  1. Development of a design flow based on a hierarchic and modular approach [1][2][3]

  2. Implementation of a  hardware file system manager distributed on different memory modules to allow graceful degradation of the system [9]

  3. Study and implementation of self checking methodologies to be applied to the memory array based on parity  [4] and signature analysis [5].

  4. Development of methodologies for fault injection in both in software and on hardware platform (System on chip) [6]  for  validating the adopted  fault tolerant methodologies [7]

  5. Formal analysis of the system in terms of reliability and data integrity [8]

  6. Hardware implementation of a prototype using FPGA based fast prototyping platforms [10][11].

 

 

Relevant publications :

  1. G.C. Cardarilli, P. Marinucci, M. Ottavi, A. Salsano, "A Fault-tolerant 176 Gbit Solid State Mass Memory Architecture", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2000, Yamanashi, Japan, pp. 173-180, October 2000.

  2. M. Ottavi, G.C. Cardarilli, P. Marinucci, S. Pontarelli, M. Re, A. Salsano, "Development of a dynamic routing system for a fault tolerant solid state mass memory", IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 2001.

  3. S. Bertazzoni, G.C. Cardarilli, D. Di Giovenale, M. Ottavi, S. Pontarelli, A. Salsano, P. Marinucci, "Sistemi elettronici tolleranti ai guasti per applicazioni spaziali", Alta Frequenza Rivista di Elettronica, vol. 13, n. 3, June 2001.

  4. G.C. Cardarilli, A. Malvoni, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, "System-on-Chip Implementation and Fault-Coverage Estimation of a Fault-Tolerant State Machine", 7th International Conference on Information Systems Analysis and Synthesis (ISAS 2001) Orlando, USA, July 2001.

  5. M. Ottavi, G.C. Cardarilli, D. Cellitti, S. Pontarelli, M. Re, A. Salsano, "Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2001, San Francisco, California, USA , October 2001.

  6. S. Pontarelli, G.C. Cardarilli, A. Malvoni, M. Ottavi, M. Re, A. Salsano, "System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2001, San Francisco, California, USA , October 2001.

  7. G.C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, R. Velazco, "Bit flip injection in processor-based architectures: a case study", 8th IEEE International On-Line Testing Workshop, IOLTW , Hotel Delos - Isle of Bendor, France , July 2002.

  8. G.C. Cardarilli, A. Leandri, P. Marinucci, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, "Design of a Fault Tolerant Solid State Mass Memory", IEEE Transactions on Reliability, vol. 52, n. 4, pp. 476-491, December 2003

  9. G.C. Cardarilli, M. Ottavi, S. Pontarelli , M. Re, A. Salsano, "A Fault Tolerant Hardware Based File System Manager for Solid State Mass Memory", 2003 IEEE International Symposium on Circuits and Systems, May 2003.

  10. G. Cardarilli, M. Ottavi, S. Pontarelli , M. Re, A. Salsano, "A Fault-Tolerant Solid State Mass Memory for Highly Reliable Instrumentation", IEEE Instrumentation and Measurement Technology Conference, Como, Italy, pp 1651 - 1656 Vol.3 May 2004.

  11. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, “A Fault-Tolerant Solid State Mass Memory for Space Applications” in IEEE Transactions on Aerospace and Electronic Systems, vol. 41, n. 4, pp: 1353-1372, October 2005

 

Prototype of the Solid State Mass Memory (University of Rome)