BOOK CHAPTERS

  1. V. Vankamamidi, M. Ottavi, F. Lombardi “Two-Dimensional Schemes for Clocking/Timing of QCA Circuits” in “Design and Test of Digital Circuits by Quantum-Dot Cellular Automata” Edts: F. Lombardi, J. Huang Artech House, Hardcover, Published November 2007
  2. V. Vankamamidi, M. Ottavi and F. Lombardi “QCA Memory” in “Design and Test of Digital Circuits by Quantum-Dot Cellular Automata” Edts: F. Lombardi, J. Huang Artech House, Hardcover, Published November 2007
  3. V. Vankamamidi, M. Ottavi, J. Huang, M. Momenzadeh and F. Lombardi “Implementing Universal Logic in QCA” in “Design and Test of Digital Circuits by Quantum-Dot Cellular Automata” Edts: F. Lombardi, J. Huang Artech House, Hardcover, Published November 2007
  4. S. Bhanja, M. Ottavi, S. Pontarelli, and F. Lombardi “QCA Circuits for Robust Coplanar Crossing” in “Emerging Nanotechnologies Test, Defect Tolerance, and Reliability” Series: Frontiers in Electronic Testing , Vol. 37 Ed. M. Tehranipoor

ARCHIVAL JOURNAL PUBLICATIONS

  1. S. Pontarelli, M. Ottavi, V. Vankamamidi, G. Cardarilli, F. Lombardi, A. Salsano “Analysis and Evaluations of Reliability of Reconfigurable FPGAs” to appear in Journal of Electronic Testing: Theory and Applications
  2. V. Vankamamidi, M. Ottavi, F. Lombardi, “Two-Dimensional Schemes for Clocking/Timing of QCA Circuits” to appear in IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems.
  3. V. Vankamamidi, M. Ottavi, F. Lombardi “A Serial Memory by Quantum-Dot Cellular Automata (QCA)” in IEEE Transactions on Computers (preprint) 26 Sept 2007.
  4. S. Bhanja, M. Ottavi, S. Pontarelli, F. Lombardi “QCA Circuits for Robust Coplanar Crossing” in Journal of Electronic Testing: Theory and Applications (JETTA) Special Issue on Test, Defect Tolerance, and Reliability of Nanoscale Devices Volume 23 , Issue 2-3 June 2007
  5. M. Ottavi, L. Schiano, D. Tougaw, F. Lombardi “HDLQ: A HDL Environment for QCA Design” in ACM Journal on Emerging Technologies in Computing Systems (JETC) Volume 2 , Issue 4 , October 2006
  6. E.P. DeBenedictis, M.P. Frank, M. Ottavi and S.E. Frost-Murphy “On the design of reversible QDCA systems” SANDIA NATIONAL LABORATORIES TECH REPORT (2006)
  7. M. Ottavi, X. Wang, L. Schiano, F.J. Meyer, Y.B. Kim, F. Lombardi, “Evaluating the Yield of Repairable SRAMS for ATE,” in IEEE Transactions on Instrumentation and Measurements October 2006
  8. M. Ottavi, S. Pontarelli, V. Vankamamidi, F. Lombardi “A QCA Memory with Parallel Read/Serial Write: Design and Analysis” in IEE Proceedings Circuits, Devices and Systems vol. 153, n. 3, pp:199 - 206, June 2006
  9. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, “Fault Localization, Error Correction and Graceful Degradation in Signed Digit Based Adders” IEEE Transactions on Computers, vol. 55, n 5, pp :534 - 540 May 2006.
  10. V. Vankamamidi, M. Ottavi, F. Lombardi. “A Line-Based Parallel Memory for QCA Implementation” in IEEE Transactions on Nanotechnology, vol. 4, n 6, pp: 690 – 698, November 2005
  11. J. Huang, M. Momenzadeh, L. Schiano, M. Ottavi, and F. Lombardi “Tile-Based QCA Design Using Majority-Like Logic Primitives” in ACM Journal on Emerging Technologies in Computing Systems (JETC) Volume 1 , Issue 3 pp: 163 – 185 October 2005
  12. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, “A Fault-Tolerant Solid State Mass Memory for Space Applications” in IEEE Transactions on Aerospace and Electronic Systems, vol. 41, n. 4, pp: 1353-1372, October 2005
  13. X. Wang, M. Ottavi, F. J. Meyer, F. Lombardi “Estimating the Manufacturing Yield of Compiler-based Embedded SRAMs” in IEEE Transactions on Semiconductors Manufacturing, vol. 18, n 3, pp: 412 – 421, August. 2005
  14. G.C. Cardarilli, F. Lombardi, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, “Comparative Evaluation of Designs for Reliable Memory Systems” in Journal of Electronic Testing: Theory and Applications, special issue "On-line Testing and Fault Tolerance", vol. 21, n. 4, pp. 429 – 444, August 2005
  15. G.C. Cardarilli, A. Leandri, P. Marinucci, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, "Design of a Fault Tolerant Solid State Mass Memory", IEEE Transactions on Reliability, vol. 52, n. 4, pp. 476-491, December 2003
  16. S. Bertazzoni, G.C. Cardarilli, D. Di Giovenale, M. Ottavi, S. Pontarelli, A. Salsano, P. Marinucci, "Fault Tolerant Electronic Systems for Space Applications" (Italian: Sistemi elettronici tolleranti ai guasti per applicazioni spaziali), Alta Frequenza Rivista di Elettronica, vol. 13, n. 3, June 2001.

REFEREED CONFERENCE ARTICLES

  1. M. Ottavi, H. Hashempuour, F. Karim, V. Vankamamidi, K. Walus, A. Ivanov “On the Error Effects of Random Clock Shifts in Quantum-dot Cellular Automata Circuits” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2007, pp. 487-498, September 2007
  2. S. Pontarelli, M. Ottavi, V. Vankamamidi, A. Salsano, F. Lombardi ”Reliability Evaluation of Repairable/Reconfigurable FPGA” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, pp. 227 – 235, October 2006
  3. M. Ottavi, S. Pontarelli, A. Leandri, A. Salsano “Design and Evaluation of an Hardware on-line Program-Flow Checker for Embedded Microcontrollers” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006 , pp 371 – 379, October 2006
  4. V. Vankamamidi M. Ottavi and F. Lombardi “Clocking and Cell Placement for QCA” in IEEE-Nano2006, pp. 343- 346, June 2006
  5. M. Ottavi, L. Schiano, S. Pontarelli, V. Vankamamidi, F. Lombardi “Timing Verification of QCA Memory Architectures” in IEEE-Nano2006, pp. 391- 394, June 2006
  6. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M.Re, A. Salsano “Localization of faults in Radix-n Signed Digit Adders” in IEEE International On-Line Testing Symposium (IOLTS 2006)
  7. S. Bhanja, M. Ottavi, S. Pontarelli, F. Lombardi, “Novel Designs for Thermally Robust Coplanar Crossing in QCA” to appear in IEEE Design and Testing in Europe 2006
  8. M. Momenzadeh, M. Ottavi, F. Lombardi “Modeling QCA Defects at Molecular-level in Combinational Circuits” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT 2005, Monterey, California, pp. 208-216, October 2005
  9. M. Ottavi, S. Pontarelli, V. Vankamamidi, F. Lombardi “Novel approaches to QCA memory design” in Proceedings of 5th IEEE Conference on Nanotechnology IEEE-NANO 2005, Nagoya, pp. 699-702 July 2005
  10. M. Ottavi, S. Pontarelli, V. Vankamamidi, A. Salsano, F. Lombardi “Design of a QCA Memory with Parallel Read/Serial Write” in Proceedings of 2005 IEEE Computer Society Annual Symposium on VLSI Tampa, Florida, pp. 292-294, May 2005
  11. M. Ottavi, S. Pontarelli, L. Schiano, G.C. Cardarilli, F. Lombardi “Evaluating Data Integrity of Memory Systems by Configurable Markov Models” in Proceedings of 2005 IEEE Computer Society Annual Symposium on VLSI Tampa, Florida, pp. 257-259, May 2005
  12. V. Vankamamidi, M. Ottavi, F. Lombardi “Tile Based Design of a Serial Memory in QCA” in Proceedings of ACM Great Lakes Symposium on VLSI Chicago, Illinois, pp. 201-206, Apr. 2005.
  13. L. Schiano, M. Ottavi, F. Lombardi, S. Pontarelli, A. Salsano, “On the Analysis of Reed Solomon Coding for Resilience to  Transient/Permanent Faults in Highly Reliable Memories”  in Proceedings of IEEE Design and Testing in Europe, Munich, Germany, pp. 580-586 Mar. 2005.
  14. X. Wang, M. Ottavi, F. Meyer, F. Lombardi, "On The Yield of Compiler-based eSRAMs", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, Cannes, France, pp. 11 – 19, October 2004.
  15. X. Wang, M. Ottavi, F. Lombardi, "Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs.", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004 , Cannes, France, pp. Pages:111 – 119, October 2004.
  16. G. Cardarilli, M. Ottavi, S. Pontarelli , M. Re, A. Salsano, "Data Integrity Evaluations of Reed Solomon Codes for Storage Systems", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, Cannes, France, pp. 158 – 164, October 2004.
  17. L. Schiano, M. Ottavi, F. Lombardi, “Markov Models of Fault-Tolerant Memory Systems under SEU ", IEEE International Workshop on Memory Technology, Design and Testing, San Jose' CA, pp. 38 – 43, August 2004.
  18. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, "A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities", Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), Funchal, Madeira Island, Portugal, pp. 141 – 146, July 2004.
  19. G. Cardarilli, M. Ottavi, S. Pontarelli , M. Re, A. Salsano, "A Fault-Tolerant Solid State Mass Memory for Highly Reliable Instrumentation", IEEE Instrumentation and Measurement Technology Conference, Como, Italy, pp 1651 - 1656 Vol.3 May 2004.
  20. M. Ottavi, L. Schiano, X. Wang,  Y.B. Kim, F. Meyer, F. Lombardi, "Yield Evaluation Methods of SRAM Arrays: a Comparative Study", IEEE Instrumentation and Measurement Technology Conference, Como, Italy, pp. 1525 - 1530 Vol.2, May 2004.
  21. M. Ottavi, X. Wang, F.J. Meyer, F. Lombardi, "Simulation of Reconfigurable Memory Core Yield", ACM Great Lakes Symposium on VLSI 2004, Boston, MA , pp. 136-140, April 2004.
  22. X. Wang, M. Ottavi, F. Lombardi, "Yield Analysis of Compiler-based Arrays of Embedded sRAMs", The 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cambridge, MA U.S.A., pp. 3-10, November 2003.
  23. G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, "Error Detection in Signed Digit Arithmetic Circuit with Parity Checker", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2003, Cambridge, MA, USA, pp. 401 – 408, November 2003.
  24. G.C. Cardarilli, M. Ottavi, S. Pontarelli , M. Re, A. Salsano, "A Fault Tolerant Hardware Based File System Manager for Solid State Mass Memory", 2003 IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, pp.V-649 - V-652 vol.5, May 2003.
  25. G.C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, R. Velazco, "Bit flip injection in processor-based architectures: a case study", 8th IEEE International On-Line Testing Workshop, IOLTW , Hotel Delos - Isle of Bendor, France , pp. 117 – 127 July 2002.
  26. S. Pontarelli, G.C. Cardarilli, A. Leandri, M. Ottavi, M. Re, A. Salsano, "A Self-Checking Cell Logic Block for Fault Tolerant FPGAs ", ISCAS 2002, Scottsdale, Arizona, USA, pp. IV-477 - IV-480 vol.4, May 2002.
  27. S. Pontarelli, G.C. Cardarilli, A. Malvoni, M. Ottavi, M. Re, A. Salsano, "System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2001, San Francisco, California, USA , pp. 455 – 460, October 2001.
  28. M. Ottavi, G.C. Cardarilli, D. Cellitti, S. Pontarelli, M. Re, A. Salsano, "Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2001, San Francisco, California, USA, pp. 403 - 411 October 2001.
  29. G.C. Cardarilli, A. Malvoni, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, "System-on-Chip Implementation and Fault-Coverage Estimation of a Fault-Tolerant State Machine", 7th International Conference on Information Systems Analysis and Synthesis (ISAS 2001) Orlando, USA, July 2001.
  30. M. Ottavi, G.C. Cardarilli, P. Marinucci, S. Pontarelli, M. Re, A. Salsano, "Development of a dynamic routing system for a fault tolerant solid state mass memory", IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, pp. 830 - 833 vol. 4, May 2001.
  31. G.C. Cardarilli, P. Marinucci, M. Ottavi, A. Salsano, "A Fault-tolerant 176 Gbit Solid State Mass Memory Architecture", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2000, Yamanashi, Japan, pp. 173-180, October 2000.

 

THESES

  1. M. Ottavi "Design and Implementation of a Solid State Mass Memory for Space Applications", Ph.D. (Dottorato) Thesis, University of Rome "Tor Vergata" 2004.
  2. M. Ottavi " Design of SDH Networks" (Italian: Progetto di Reti SDH), M.Sc. (Laurea)  Thesis, University of Rome "La Sapienza" 1999.
     

ORAL PRESENTATIONS

  1. “Modeling QCA Defects at Molecular-level in Combinational Circuits” at IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2005 Monterey, October 2005
  2. “Tile Based Design of a Serial Memory in QCA” at ACM Great Lakes Symposium on VLSI Chicago, Illinois, Apr. 2005.
  3. "On The Yield of Compiler-based eSRAMs",  at IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, Cannes, France, October 2004.
  4. "Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs.", at IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004 , Cannes, France, October 2004.
  5. "Data Integrity Evaluations of Reed Solomon Codes for Storage Systems", at IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, Cannes, France, October 2004.
  6. "Yield Analysis of Compiler-based Arrays of Embedded sRAMs",  at The 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cambridge, MA U.S.A, November 2003.
  7. "Bit flip injection in processor-based architectures: a case study", at 8th IEEE International On-Line Testing Workshop, IOLTW , Hotel Delos - Isle of Bendor, France, July 2002.
  8. "System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology", at IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2001, San Francisco, California, USA,  October 2001.
  9. "Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines", at IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2001, San Francisco, California, USA, October 2001.
  10. “Fault-Tolerance and Fault injection on reprogrammable COTS (SOC and FPGA)” (Italian: Fault-Tolerance e Fault injection su COTS riprogrammabili (SOC e FPGA)) at GE (Gruppo Elettronica) meeting, June 2001

POSTERS

  1. “Design of a QCA Memory with Parallel Read/Serial Write”  at 2005 IEEE Computer Society Annual Symposium on VLSI Tampa, Florida, May 2005
  2. “Evaluating Data Integrity of Memory Systems by Configurable Markov Models” at 2005 IEEE Computer Society Annual Symposium on VLSI Tampa, Florida, May 2005
  3. Development of a dynamic routing system for a fault tolerant solid state mass memory", at IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 2001.