WORK EXPERIENCE:

  1. University of Rome "Tor Vergata" Rome, Italy  (October 2009 – Present)
    Research Professor
  2. Advanced Micro Devices Boxborough, MA (March 2007 – August 2009)
    Senior Design Engineer
  3. Northeastern University Boston, MA (October 2006 – February 2007)
    Post doctoral research fellow
  4. Sandia National Laboratories Albuquerque, NM (June 2006 – September 2006)
    Post doctoral research fellow
  5. Northeastern University Boston, MA (May 2004 – June 2006)
    Post doctoral research fellow
  6. University of Rome "Tor Vergata" Rome, Italy  (November 2000 - February 2004)
    Ph.D. student     (R.A. and T.A. activity)
  7. Northeastern University Boston, MA (March 2003 - December 2003)
    Visiting Researcher 
  8. Consorzio Ulisse Rome, Italy (January 2000 - December 2000)
    Digital systems designer
 

EDUCATION:

Ph.D. (Dottorato):

February 2004, Microelectronic & Telecommunications Engineering
Tile of dissertation: “Design and Implementation of a Solid State Mass Memory for Space Applications”
Department of Electronic Engineering
 University of Rome "Tor Vergata"
Rome, Italy.

M.Sc. (Laurea):

December 1999, Electronic Engineering
Title of dissertation: “Design of SDH Networks”
Department of Electronic Engineering
 University of Rome "La Sapienza"
Rome, Italy.

 

RESEARCH INTERESTS:

 

AFFILIATION AND PROFESSIONAL ACTIVITIES:

Member of IEEE
Member of Gruppo Elettronica – GE (The Italian Group of Electronics)
Member of Test and Reliability Group, Northeastern University
Member of Microelectronics Lab Research Group, University of Rome "Tor Vergata"
Served as reviewer for: IEEE Design and Test Magazine, IEEE Transactions on VLSI Systems, IEEE                                 Transactions on Computers, IEEE Transactions on Reliability, Journal of Electronic Testing: Theory and Applications,               IEEE SOC Conference.
Publicity chair of the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06)
Attended and given presentations at several IEEE Sponsored Meetings.

 

TEACH ASSISTANCE AND SEMINARS:

University of South Florida

2005: Invited Seminar: "Memory Architectures for Quantum-dot Cellular Automata"

University of Rome "Tor Vergata"

2004: Invited Seminar: "Design and Development of a Mass memory for Space Applications" at Master Spazio

2002: TA in course of Laboratory for Informatics Applications (Italian: Laboratorio di Applicazioni Informatiche)

2002: Seminar: "Introduction to VHDL language" (in Digital Electronics course)

2002: TA in course of Programmable Electronic Systems (Italian: Sistemi Elettronici Programmabili)

2001-2002: TA in course of Digital Electronics (Italian: Elettronica Digitale)

CEFRIEL Politecnico of Milan

2002: Invited Lesson: Techniques for Fault Detection and Correction in Microprogrammed Architectures " (Italian: Tecniche Di Rilevazione e Correzione di Guasti su Strutture Microprogrammate) at “Corso di Perfezionamento Post-Laurea”

 

GRADUATE STUDENTS CO-SUPERVISION:

Master (Laurea) Degree with thesis:

  1. D. Cellitti: “Design and development of a hardware module for the management of a fault tolerant file system” (Italian: Progettazione e sviluppo di un modulo hardware per la gestione di un file system fault-tolerant) – University of Rome “Tor Vergata” Advisor Prof G.C. Cardarilli 2001
  2. A. Leandri: “Design of a Fault Tolerant hardware/software control system of a Solid State Mass Memory ” (Italian: Progettazione di un sistema hardware/software fault-tolerant per il controllo di una memoria di massa allo stato solido (SSMM)). - University of Rome “Tor Vergata” Advisor Prof G.C. Cardarilli 2002
  3. G. Bufalini: “Design and hardware implementation of a router for high speed serial communication protocols” (Italian: Progettazione e implementazione hardware di un router per protocolli seriali ad alta velocita') - University of Rome “Tor Vergata” Advisor Prof G.C. Cardarilli 2003

Ph.D. Degree

  1. M. Momenzadeh  “Defect Tolerance of QCA Systems at Nano Scale” Northeastern University, Member of dissertation committee: May 2006
 

FUNDED RESEARCH:

 

TECHNICAL SKILLS:

  1. Programming languages: C, C ++, Perl, Fortran, Pascal
  2. Hardware Description Languages: VHDL, Verilog
  3. Hardware platforms and instrumentation: FPGAs (Xilinx and Altera), Microcontrollers (general knowledge and experience on Intel 8051 architecture), Oscilloscopes, Logic Analyzers, Signal Sources.
  4. Operative Systems: UNIX (Linux, Solaris),  Windows
  5. Engineering Applications: Spice, XILINX ISE FPGA tool, Matlab, Active HDL, Modelsim.
  6. Text formatting: LATEX, HTML, CSS
  7. Others: MS Office, UNIX/Linux application programs
 

LANGUAGES: