Enqiang Sun

Office: 225 Egan Research Center
Phone: (617) 373-7349
Email: esun AT ece.neu.edu

About me

Education

• Phd in Computer Engineering, Northeastern University, Expected
  
• MS in Electrical and Computer Engineering, Northeastern University, 2009
  
• BE in Electrical Engineering, Shanghai Jiao Tong University, 2001
  

Research Areas

• GPGPU: Programming Model on Heterogeneous Platform, High Performance Computing
  
• Parallel Computing: Aggressive Software Value Prediction on GPU
  
• Binary Translation and Instrumentation
  

Publications and Patents

• "Platform-Oblivious Heterogeneous Multi-threaded Programming Model"
  Enqiang Sun and David Kaeli
  Submitted to the 27th IEEE International Parallel & Distributed Processing Symposium
  
  
• "Enabling Task-level Scheduling on Heterogeneous Platforms" (PDF)
  Enqiang Sun, Dana Schaa, Richard Bagley, Norman Rubin and David Kaeli
  Proceedings of the 5th Workshop on General Purpose Processing on Graphics Processing Units(GPGPU5)
  conducted in conjunction with the 17th International Conference on Architectual Support for Programming Languages and Operating Systems (ASPLOS 2012), London, UK, Mar. 2012
  Acceptance rate: 37% (13/35)
  
  
• "Aggressive Value Prediction on a GPU" (PDF)
  Enqiang Sun and David Kaeli
  Expanded version of SBAC-PAD 2011 paper
  International Journal of Parallel Programming, November 2012
  
  
• "Aggressive Value Prediction on a GPU" (PDF)
  Enqiang Sun and David Kaeli
  Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing(SBAC-PAD), Vitoria, ES, Brazil, Oct. 2011
  Acceptance rate: 34% (26/76)
  
  
• "A Binary Instrumentation Tool for the Blackfin Processor" (PDF)
  Enqiang Sun and David Kaeli
  Proceedings of the Workshop on Binary Instrumentation and Applications(WBIA '09),
  conducted in conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (Micro-42), New York City, NY, Dec. 2009
  
  
• "A Binary Instrumentation Tool for the Blackfin Processor"
  Master Thesis, Aug. 2009
  
  
• "Electric Circuit for Testing Read-Only Memory"
  with Weibing Shang and Yiyan Yin
  Chinese Patent Publication No. CN 2615770 Y, Published on 05/12/2004
  
  
• "Circuit for Testing Read-Only Memory and Testing Method thereof"
  with Weibing Shang and Yiyan Yin
  Chinese Patent Publication No. 1553326, Published on 12/08/2004
  
  

Work Experience

• AMD, Graphics Product Group, Boxborough, MA USA
  Co-op Engineer, Feb. ~ Jun. 2011
  Developing extensions to OpenCL to allow for significant speedup when programs run on systems containing multiple GPU and CPU devices from different vendors
  
  
• Analog Devices, Platform Tools Group, Norwood, MA USA
  Graduate Intern, Jul. ~ Dec. 2008
  Participated in software design and unit/integration/system testing of Analog Devices' VisualDSP++ 5.0; Developed and maintained the overnight regression testing framework for the System Builder Project
  
  
• EPSON Electronics, Shanghai Research Center, Shanghai, China
  Hardware Design Engineer, Aug. 2004 ~ Aug. 2006
  Participated in the design of low-power RISC embedded processors, including logic module RTL design, module simulation/verification and gate count estimation
  
  
• Huayuan Microelectronics, Shanghai Research Center, Shanghai, China
  Hardware Design Engineer, Aug. 2001 ~ Jul. 2004
  Collaborated and participated in the projects of digital circuit design; Familiar with VLSI design flow from front-end logic modules RTL design/simulation/verification/synthesis to the back-end place&route/layout/LVS/DRC
  
  

Awards

• Travel Grant for 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2012), London, UK, Mar. 2012
  
• Travel Grant for 42nd International Symposium on Microarchitecture Conference (Micro-42), New York City, NY, Dec. 2009
  
• Academic Merit-Based Scholarship, Shanghai Jiaotong University, 1997 - 2000
  
• University Soccer Champion, Shanghai Jiaotong University, 1998
  
• University Soccer Runner-up, Shanghai Jiaotong University, 1999
  

Activities

• Editor: Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units
  
• Reviewer: GPGPU3
  
• External Reviewer: IEEE Transactions on VLSI Systems
  
• IEEE graduate student member
  
• ACM graduate student member
  

Northeastern University
Dept. of Electrical and Computer Engineering