BYUNGHYUN JANG Ph.D Candidate in Computer Engineering (GPA 3.9/4.0)   Advisor: Prof. David Kaeli   Computer Architecture Group (NUCAR)   Department of Electrical and Computer Engineering   Northeastern University, Boston MA U.S.A. Education   MS in Computer Science (2001~2002), Oklahoma State University, U.S.A.     (GPA 3.8/4.0 - 36 credits)   BS in Bio-Mechatronics Eng. (1993~2000), Sungkyunkwan University, South Korea     (GPA 3.69/4.5 - 142 credit) Research Areas   · GPU Computing (GPGPU)   · Program Parallelization for Data Parallel Architectures   · High Performance Parallel Computing (Programming Models and Languages)   · Computer Architecture and Compiler Work Experience   · AMD, Graphics Compiler Group, Marlborough MA U.S.A., Intern, Jan.~Jun. 2008   · Samsung Electronics, Digital Media R&D Center, South Korea, Full Time Research Engineer,     2003~2005   · Samsung Electronics, Digital Media R&D Center, Suwon, South Korea, Intern, Jun.~Jul. 2002 Awards   · AMD/ATI Fellowship Award, 2008~2009   · Best Poster Award, Research & Industrial Collaboration Conference (RICC), 2008 and 2009 in a row   · World First Digital Multimedia Broadcasting (DMB) Solution Development Award,     Samsung Electronics, 2004   · Academic Merit Based Scholarship, Sungkyunkwan University, 1998~1999 Publications (Conference and Journal) [12] Modifying Memory Access Patterns using Data Transformations for Loop Vectorization on Multithreaded Vector GPU Architectures, submitted to Workshop on Language, Compiler, and Architecture Support for GPGPU (LCA-GPGPU), Bangalore, India, 2010 [11] Exploiting Memory Access Patterns to Improve Memory Performance in Data Parallel Architectures, submitted to IEEE Transactions on Parallel and Distributed Systems (TPDS), 2010 [10] Data Transformation Enabling Loop Vectorization on Multithreaded Data Parallel Architectures, to appear 15th ACM SIGPLAN Symposium on Principles and Practices of Parallel Programming (PPoPP'10), Bangalore, India, 2010 [9] Profile-Guided Optimization of Critical Medical Imaging Algorithms, IEEE International Symposium on Biomedical Imaging (ISBI'09), Boston MA, Jun. 2009 [8] Multi GPU Implementation of Iterative Tomographic Reconstruction Algorithms, IEEE International Symposium on Biomedical Imaging (ISBI'09), Boston MA, Jun. 2009 [7] Architecture-Aware Optimization Targeting Multithreaded Stream Computing, 2nd Workshop on General Purpose Computation on GPU (GPGPU2), Washington DC, Mar. 2009   - Past Research - [6] Monomer Control for Error Tolerance in DNA Self-Assembly, Journal of Electronic Testing: Theory and Application (JETTA), 2007 [5] Modeling and Evaluation of Multi-Bank SRAM Design for Leakage Power Reduction, Proceedings of the 4th Boston Area Computer Architecture Workshop (BARC'07), 2007 [4] Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling, Design Automation and Test in Europe (DATE'07), 2007 [3] Error Tolerance of DNA Self-Assembly by Monomer Concentration Control, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), Washington DC, Oct. 2006 [2] Spare Line Borrowing Technique for Distributed Memory Cores in SoC, Special Session, IEEE Instrument and Measurement Technology Conference (IMTC'05), Ottawa, Canada, May. 2005 [1] Modeling and Evaluation of the Interconnection-driven Repairability for Distributed Embedded Memory Cores on System-on-Chip, International Conference on Modeling, Identification, and Control (MIC'03), IASTED, Innsbruck, Austria, Feb. 2003 Presentations and Invited Talks   [12] CUDA and OpenCL tutorial, Workshop on GPU Computing for Biomedical Research,          Harvard Medical School, Oct. 2009   [11] Exploiting Memory Access Patterns to Improve Memory Performance in Data Parallel          Architectures, AMD, Boxborough MA, Oct. 2009   [10] CUDA Tutorial, CRA-W/CDC Careers in High Performance Systems (CHiPS) Mentoring          Workshop, UIUC, Jul. 2009   [9] AMD Stream Computing, Northeastern University Computer Architecture Group (NUCAR), 2009   [8] Shader, Northeastern University Computer Architecture Group (NUCAR), 2009   [7] Instruction Scheduling for Minmal Register Usage in Multithreaded VLIW GPU, Shader Compiler        Group, AMD/ATI, 2008   [6] Hardware Performance Counter and Toss Point in SIMD GPU Machine, Shader Compiler Group,        AMD/ATI, 2008   [5] Register Allocation and Performance in SIMD GPU Machine, Shader Compiler Group, AMD/ATI,        2008   [4] CUDA Programming, Northeastern University Computer Architecture Group (NUCAR), 2007   [3] Binary Translation, Northeastern University Computer Architecture Group (NUCAR), 2007   [2] Decompilation, Northeastern University Computer Architecture Group (NUCAR), 2007   [1] Linker and Loader, Northeastern University Computer Architecture Group (NUCAR), 2007 * Detailed resume and references are available upon requests via email at * Redesigned on 5/18/2009