The goal of this workshop is to provide a forum for researchers and practitioners from industry and academia to discuss advances in technology, architecture, and algorithms that address the growing gap between CPU/network and memory speeds. Both hardware and software approaches to addressing this speed gap are encouraged.

We are especially interested in attracting new, experimental or paper techniques, technologies and algorithms that address this issue. Note, we discourage papers that simply provide yet a new incremental improvement to cache performance.

• Erik Altman, IBM Research
• Jean Loup Baer, University of Washington
• Brad Calder, UC San Diego
• Tien-Fu Chen, National Chung Cheng University
• Bruce Cockburn, University of Alberta
• Duncan Elliott, University of Alberta
• Michael Foster, NSF
• Antonio Gonzalez, UPC
• Lizy John, University of Texas, Austin
• Mark Johnson, Naval Research Lab
• Artur Klauser, Compaq
• Fabrizio Lombardi, Northeastern University
• Sally McKee, University of Utah
• Waleed Meleis, Northeastern University
• Trevor Mudge, University of Michigan
• Shubu Mukherjee, Compaq
• Walid Najjar, Colorado St.
• Laurence Sadwick, University of Utah
• Andre Seznec, IRISA
• Per Strenstrom, Chalmers University
• Gary Tyson, University of Michigan
• Augustus Uht, University of Rhode Island