Vilas Sridharan
vilas dot sridharan at gmail dot com
617-877-3868
EDUCATION:
Expected Graduation May 2009
Ph.D. Candidate in Computer Engineering (Computer Architecture)
Research Includes:
Reliability modeling and approaches to soft error rate estimation in simulation.
Micro-architectural and architectural approaches to error detection, prevention, and recovery.
Graduated January 2007
M.S.E in Computer Engineering
GPA: 3.92 / 4.0
Thesis: Soft Errors in Cache Memory
Graduated May 2000
B.S.E. Electrical Engineering with Honors
GPA: 3.67 / 4.0 (departmental)
EXPERIENCE:
Advanced Micro Devices, Processor Design - Intern
Fort Collins, CO and Boxborough, MA
May 2007 - August 2007
Derived reliability estimates and standardized methodology to calculate error rates for AMD processors.
Implemented simulation infrastructure to aid in soft error modeling of future processors.
Intel Corporation, Fault Aware Computing Technologies - Intern
Hudson, MA
January 2006 - July 2006
Helped to implement detailed simulation framework to analyze the effects of soft errors.
Performed detailed error rate analysis and helped derive and analyze new methods for error prevention.
Sun Microsystems, SPARC Server Division - CPU Bring-up Engineer
Camberley, United Kingdom
July 2003 - August 2004
Logical and Electrical bringup and debug of high-performance dual-core processor for server systems.
Participated in design of bringup system for Niagara, a multi-threaded, multi-core SPARC processor and server.
Sun Microsystems, High-End Entry Servers - Board Designer
Burlington, MA
August 2000 - July 2003
Board and system-level design for SPARC server systems.
Gained experience with logical and electrical aspects of several industry-standard bus technologies.
Includes system (cache coherency) buses, memory buses, and IO buses.
Debug and validation of high-performance SPARC processors including logical and electrical issues.
PUBLICATIONS:
See full list of publications here.
References available upon request.