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1)
M. Fayyazi, D. Kaeli, W. Meleis, "Linear-Time Parallel
Algorithms for Maximum Weight Bipartite Matching," submitted to
ACM Symposium on Parallelism in Algorithms and Architectures
(SPAA'05).
2)
M. Fayyazi, D. Kaeli, W. Meleis, "An Adjustable Linear Time
Complexity Parallel Maximum Weight Bipartite Matching Algorithm,"
submitted to Information Processing Letters.
3) M. Fayyazi, N.
Rubin,
C. Reeve, "Integrating
Splitting Transformations into an ILP Instruction Scheduler,"
Technical Report, ATI Research Inc., Marlborough, Massachusetts, August
2004.
4) M. Fayyazi, D. Kaeli, W. Meleis, "Parallel
Maximum Weight Bipartite Matching Algorithms for Scheduling in
Input-Queued Switches," IEEE International Parallel and
Distributed Processing Symposium (IPDPS 2004), pp. 26-30, Santa Fe, New
Mexico, April 2004.
5) M. Fayyazi, D. Kaeli, Z. Navabi, "Dynamic
Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet
Packet Switching," International Conference on Parallel and
Distributed Processing Techniques and Applications (PDPTA 03),
vol. 2, pp. 819-823, Las Vegas, Nevada, June 2003.
6) M. Fayyazi, D. Kaeli, "Localized
Message Passing Structure for High Speed Ethernet Packet Switching,"International
Conference on Parallel and Distributed Processing Techniques and
Applications (PDPTA 02), pp. 1551-1557, Las Vegas, Nevada, June 2002.
7)
M. Fayyazi, D. Kaeli, "A Study of DSP and Microcontroller Applications
on FRIO DSP," Technical Report, Analog Devices Inc., Norwood,
Massachusetts, July 2001.
8)
M. Fayyazi, Z. Navabi, "Accelerating
Test Generation by VLSI Hardware Emulation," 9th IEEE North
Atlantic Test Workshop, pp. 84-89, Gloucester, MA, May 2000.
9) P. J. Drongowski, D. Hunter, M. Fayyazi, D. Kaeli, J. Casmira,
"Studying the Performance of the FX!32 Binary Translation System,"
in the Proceedings of the 1st IEEE Workshop on Binary Translation , Newport
Beach,CA,
October 1999.
10) P. A. Riahi, M. R. Movahedin, M. Fayyazi, "Core Architecture of
UTS-DSP Processor," ICEE'99, Tehran,Iran,
June 1999.
11) M. Fayyazi, M. R. Movahedin, Z. Navabi, P. A. Riahi, A. G. Dezfoli,
"An Efficient CPU Architecture for DSP
Processors," ICEE'99, Tehran, Iran, June 1999.
12) M. Fayyazi, Z. Navabi, "Using VHDL
Neural Network Models for Automatic Test Generation," 2nd
Workshop on Libraries, Component Modeling, and Quality Assurance, Toledo,Spain,
April 1997.
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