Before I came to Northeastern University to continue my education, I worked in Silicon Valley, CA for more than 4 years. There, I was able to successfully complete numerous projects with Cadence Design Systems and Pluris Terabit Networks, starting with the conceptual stages to following through on full scale production. I am accustomed to efficiently working in design teams, as well as researching advanced topics on my own.
Currently, I am a Research Assistant in Northeastern's University Computer Architecture Research Group (NUCAR) under the supervision of Professor David Kaeli.
If you are interested in my qualifications for a potential position in your company, please email me. I am looking forward to hearing from you.
Below, you'll find my resume in both Word and PDF formats:
Resume in Microsoft Word format
Resume in Adobe PDF format
Otherwise, here is a HTML version:
DARREN NG
Email: dng@ece.neu.edu
Master of Science in Computer Engineering Candidate 08/04
· Awaiting completion of Master Thesis
Bachelor of Science in Electrical Engineering 05/98
Northeastern University Computer Architecture Research Group (NUCAR) 01/03-Present
Research
Assistant
Northeastern University, Boston, MA, 02115
·
Currently researching the
implementation and performance impact of dynamic garbage
collector refactoring in
the IBM Jikes Research Virtual Machine (RVM) using AspectJ.
·
Reverse engineered the underlying
software hierarchy of Friend, an integrated analytical
front-end application
for bioinformatics, using aspect oriented programming (AOP).
· Presented technology and research updates to NUCAR members on a continual basis.
Research and Development – Network Systems Design 02/01-07/02
Pluris Terabit Networks, Cupertino, CA, 95014
·
Wrote the processor and
statistical block Verilog code in Pluris’ second generation network
processor
ASIC – NP10.
·
Created Pluris’ Very Short Reach
(VSR) 10 Gigabit transponder utilizing 12 channel by
1.25 Gigabit Vertical
Cavity Surface Emitting Laser (VCSEL) optics.
·
Specified and designed the
PowerPC 755 microprocessor section and corresponding
Virtex-2 device support /
administration FPGA on the 10 Gigabit Ethernet line card.
· Analyzed and modeled the 10 Gigabit Ethernet line card’s post route static signal timing.
· Identified and corrected system reliability faults on OC48/192 line and fabric cards.
Research and Development– Digital Hardware Design 06/98-02/01
Cadence Design Systems – Quickturn Emulation Division, San Jose, CA, 95131
· Co-wrote the Dynamic Interconnect test section in Quickturn’s emulator patent.
·
Designed and fully documented
Quickturn’s new 20-layer, impedance and crosstalk controlled
Backplane Cable
Board (BCB) and related accessories.
· Created and implemented the BCB JTAG controller utilizing a Xilinx 4K XLA FPGA.
· Collaborated with Firmware and Manufacturing to create the BCB diagnostics.
·
Improved emulator performance
with a memory cornerturn FPGA design that increased trace
data uploads by 300%
and vector data downloads by 200%.
· Debugged and improved Quickturn’s Mercury/Mercury Plus emulator reliability.
·
Developed a software database
program that utilized a high degree of data coupling and
functional cohesion
for extreme stability and reuse.
· Designed and simulated a pipelined MIPS using VHDL models and Viewlogic tools.
· Profiled application characteristics using ATOM - Analysis Tools with Object Modules
· Program Comprehension Using Aspects
- Accepted at the International Conference on Software Engineering WoDiSEE 2004
· Eta Kappa Nu - Electrical Engineering Honor Society
· IEEE - Institute of Electrical and Electronics Engineers
Programming Languages:
C++, Java, AspectJ, Perl, Visual Basic, and HTML
Hardware Description Languages:
Spice, VHDL, Verilog, and Verilog XL
Hardware and Programmable Logic Design Tools:
Innoveda Electronic
Design Tools, ADI Xpro, Xilinx Foundation Suite, Altera Quartus II, Synplicity,
Cadence Allegro, and Spectra Quest