Objectives:

Automatic design and verification of complex digital systems with Verilog is the main course objective.  Using Verilog for a design that consists of several parts that include controllers, sequential and combinational parts is focused.  Students will learn details of hardware of processor architectures and their peripherals. Testbench development and assertion verifications will be discussed.

Description:

The course covers automated design, verification, and synthesis of digital systems with the standard Verilog hardware description language emphasizing on CPU structures and interfacing.  Course shows how Verilog can be used for simulation, assertion verification, synthesis and test of digital systems.  Hardware description using predefined parts, using the bussing structure of a system or using a mapping of inputs to outputs will be discussed.  Verilog constructs for representation and modeling of VLSI parts and components, basic CMOS gates, complex gates, static and dynamic flip-flops and latches will be presented and their switch level representation in Verilog will be discussed.  After a complete presentation of the Verilog language, synthesizability concepts and templates for logic unit, memory unit, and state machine synthesis will be presented.  The course continues by using Verilog in a complete design and description of a CPU, its peripheral devices, and generation of a complete CPU board.  In the discussion of the CPU, various forms of controllers, stack, and addressing modes will be discussed and corresponding Verilog code will be presented.  Caching and alternatives in cache hardware and replacement algorithms will be discussed by presenting their Verilog code.  Bus arbitration and multiple use of system busses will be demonstrated by presenting a DMA system for the CPU and interfacing it with the CPU.  All presentations will lead to a complete Verilog code for a CPU board.  A test-bench in Verilog will be developed that will read machine code, apply it to the CPU board and monitor flow of data in system components and busses.

Course Material:

Main Text: “Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verification”; 2006; McGraw Hill Text; ISBN: 0070144564-1.  Can be purchased from Amazon.com.
 

Reference: “IEEE Std. 1364, Hardware Description Language Based on the Verilog Hardware Description Language,” IEEE, New Jersey, 1995.

Homeworks:

Six computer assignments.  Structural design, Pin-to-Pin, Bussing and data-flow, Complete system description and verification, CPU implementation, Adding a peripheral.

Lecture 1:

·         Introduction

o       Course Contents

o       Goals

o       Course Procedures

·         Digital System Design Automation with Verilog

o       Digital Design Flow

o       Verilog HDL

Lecture 2:

·         Register Transfer Level Design with Verilog      

o       RT Level Design

o       Elements of Verilog

o       Component Description in Verilog

o       Testbenches

Lecture 3:

·         Tools and Environments

o       HDL Simulation

o       Design Entry

o       Pre-synthesis Simulation

o       Synthesis

o       Post-Synthesis Simulation

Lecture 4:

·         Verilog Language Concepts

o       Characterizing Hardware Languages

o       Module Basics

o       Verilog Simulation Model

o       Compiler Directives

o       System Tasks and Functions

Lecture 5-6:

·         Combinational Circuit Description

o       Module Wires

o       Gate Level Logic

o       Hierarchical Structures

o       Describing Expressions with Assign Statements

o       Behavioral Combinational Descriptions

o       Combinational Synthesis

·         Exam Review

Lecture 7:

·         Midterm Exam

o       Verilog HDL

o       Simulation Model

o       Tools

o       Combinational Circuits

Lecture 8-9:

·         Sequential Circuit Description

o       Sequential Models

o       Basic Memory Components

o       Functional Registers

o       State Machine Coding

o       Sequential Synthesis

Lecture 10:

·         Component Test and Verification

o       Testbench

o       Testbench Techniques

o       Design Verification

o       Assertion Verification

o       Text Based Testbenches

Lecture 11:

·         Detailed Modeling

o       Switch Level Modeling

o       Strength Modeling

Lecture 12:

·         RT Level Design and Test

o       Sequential Multiplier

o       von Neumann Computer Model

Lecture 13:

·         RT Level Design and Test

o       CPU Design and Test

o       Processor RTL Architecture

o       CPU Testing

o       Text Based Testing

Lecture 14:

·         Processor Devices

o       Cache

o       Serial Interface

o       DMA