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Verilog: The Language, System Design and Synthesis (Series)

 

Verilog for Design and Simulation of Digital Systems
 Synthesis of Digital Systems with Verilog

 


                                                                                 Verilog: The Language, System Design and Synthesis (Series)


PRESENTER:

Dr. Zainalabedin Navabi is an adjunct professor of electrical and computer engineering at Northeastern University. Dr. Navabi is the author of the textbook, VHDL: Analysis and Modeling of Digital Systems, 1993, 1998 McGraw-Hill, and the 1999 book, Verilog Digital System Design. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages (HDL). He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL courses at Northeastern University in 1989. Since then he has conducted many short courses and tutorials on this subject in the United States and abroad. In addition to being a professor, he is also a consultant to CAE companies. Dr. Navabi received his Ph.D. from the University of Arizona in 1981. He is a senior member of IEEE, and a member of IEEE Computer Society, ACM, ASEE and Euromicro.


COURSE DESCRIPTION:

 This series of Verilog training courses aims to teach the design and implementation of digital systems using the Verilog HDL. The first course presents basics and elements of Verilog through use of simple examples. By use of point-examples, constructs of the language and their applications will be discussed. After presentation of this introductory material, the course continues with top-down design with Verilog. In this part, complete examples including bussing and hard-wired controllers will be designed with the aid of Verilog. This course includes an online demonstration of a Verilog simulation tool environment. The second course presents Verilog for synthesis of digital systems. We begin with presenting point-examples illustrating various constructs of Verilog and how they synthesize to hardware. We will then present a complete digital system which will be described and synthesized into simulatable library components. Using a commercial synthesis tool, an online demonstration shows steps that are involved in synthesizing with Verilog.


For the use of simulation and synthesis tools on Northeastern University computers, students will be issued access codes, provided they register at least two week in advance. Lecture slides provide a complete reference for the material that is presented. In addition, Northeastern University web pages include Verilog code for all examples that are being presented plus a complete set of other examples covering all hardware description aspects. The 1999 McGraw-Hill book, Verilog Digital System Design, discusses topics covered in these courses in greater detail, and is recommended for the series. The book is available in most local bookstores, from McGraw-Hill publishing Inc., or from www.amazon.com.


This series can benefit engineers in migrating from conventional design methodologies to using Verilog for design and implementation of complex digital systems, or beginner engineers who are familiar with digital system design techniques and need to use Verilog in their hardware design projects.


INTENDED AUDIENCE:

 This series is intended for engineers, scientists, and instructors who are already familiar with digital system design.


SCHEDULE: Three live, 6-hour broadcasts


 SPONSOR: Northeastern University


CEU: 1.5

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