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Electrical and Computer Engineering
Department
NU: ECE 3401
NTU: DS 765-F
Digital System Design
with Hardware Description Languages
Summer 2002
Course Description and
detailed Outline
4:00-5:40 PM Tue, Thr
This course
covers the standard VHDL 1076-1993 hardware description
language. Using this language for
design, description and synthesis of hardware is emphasized. We
discuss structural, dataflow and behavioral levels of
abstraction and emphasize on RTL synthesizable code. The
complete VHDL language is discussed using actual design
examples. We discuss IEEE standards and show how the standard
logic, numeric and arithmetic packages can be used to simplify
description of synthesizable code in VHDL. In the second part of
the course we present VHDL code of a RISC processor. We use the
IEEE standard packages for the description of this CPU and show
the complete code of this CPU for synthesis and programmable
logic programming. An existing cross assembler will be linked
with the CPU VHDL description to demonstrate an actual design
and implementation environment. For the interface to the CPU
memory, the standard TEXTIO package is used. The completed
design illustrates top-down design procedure for a complex
design. After completing this course you will be able to write
efficient VHDL code for simulation and synthesis. You will be
able to partition a large design for top-down simulation and
synthesis in VHDL. You will learn the use of VHDL simulation and
synthesis as well as programmable device programming
environments.
Ref1:
"VHDL:
Analysis and Modeling of Digital Systems,"
Zainalabedin Navabi, McGraw-Hill Publishing Inc., New York,
1998.
LECTURE 1:
June
18, 2002, CHAPTER 1, Ref. 1: HOMEWORK: none;
Topics are: Introduction, HDLs, Simulation,
Synthesis, CAD environments.
LECTURE 2:
June 20,
2002, CHAPTER 2-3, Ref. 1:
HOMEWORK#1: (CHAP 3) TBA
[No Simulation Required]
[Due: Midnight, June
30, 2002].
Topics are: VHDL
history, evolution, design strategy, levels of abstraction, VHDL
overview, the general structure of the language.
Top-down design strategy, An example
design flow, VHDL overview.
LECTURE 3:
June 25,
2002,
CHAPTER 3-4, Ref. 1;
Topics are:
VHDL timing, concurrency, sequentially.
LECTURE 4:
June 27,
2002,
CHAPTER 4, Ref. 1: HOMEWORK#2:
(Chap 4) TBA [No Simulation Required]
[Due:
Midnight, July 7, 2002];
Topics are:
Timing, Delay modeling, Transactions, Sequential placement of
transactions, Events and event handling.
LECTURE 5:
July
2, 2002,
CHAPTER 5, Ref. 1: HOMEWORK: none.
Topics are: Structural descriptions in VHDL,
Binding alternatives, design of flip-flops, iterative
structures.
LECTURE 6:
July
9, 2002,
CHAPTER 5, Ref. 1: HOMEWORK#3:
(Chap 5) TBA
[Due: Midnight, July
21, 2002];
Topics are:
Design configuration, configuration specification, binding.
LECTURE 7:
July
11, 2002,
CHAPTER 6, Ref. 1: HOMEWORK: none.
Topics are: Design organization, subprograms,
number conversion, packages
LECTURE 8:
July
16, 2002,
CHAPTER 6, Ref. 1: HOMEWORK#4:
(Chap 6) TBA
[Due: Midnight, July
28, 2002; extended
to August 4]
Topics are:
Design parametrization, configuration declaration, binding
alternatives, Std_logic.
LECTURE 9: July
18, 2002,
CHAPTER 7, Ref. 1: HOMEWORK: none.
Topics are: Types, Arrays, Physical types,
overloading
LECTURE 10:
July
23, 2002,
CHAPTER 7, Ref. 1: HOMEWORK#5:
(Chap 7) TBA
[Due: Midnight,
August 4,
2002];
Topics are:
Overloading, attributes, user attributes
LECTURE 11: July
25, 2002,
CHAPTER 8, Ref. 1: HOMEWORK: none.
Topics are: Modeling selection logic, block
statements, clocked flip-flops, latches
LECTURE 12:
July
30, 2002,
CHAPTER 8, Ref. 1: HOMEWORK#6:
(Chap 8)
[Due: Midnight, August 11,
2002];
Topics are:
State machines, multiple active states, open collector gates
LECTURE 13:
August 1,
2002,
CHAPTER 9, Ref. 1: HOMEWORK: none.
Topics are:
Process statements, text IO, State machines,
LECTURE 14:
August 6, 2002,
CHAPTER 9, Ref. 1: HOMEWORK#7:
(Chap 9)
[Due: Midnight, August 18,
2002];
Topics are:
Handshaking, Other forms of state machines, a top-down design
LECTURE 15:
August
8, 2002,
CHAPTER 9, Ref. 1: HOMEWORK#8:
[Due:
Midnight, August 19,
2001];
Topics are:
Overflow absorber, design strategy, logic and state machine
synthesis.
MIDTERM EXAM:
August 9, 2002,
CHAPTERS 1 through 9.1.
LECTURE 16:
August
13, 2002,
CHAPTER 10, Ref. 1: HOMEWORK: none.
Topics are:
Defining V8
URISC CPU, timing, utilities, behavioral description,
partitioning, sub-components.
LECTURE 17:
August 15, 2002,
CHAPTER 10, Ref. 1: HOMEWORK#9: Part a Will be
Emailed [Due:
Midnight, August 25, 2002];
Topics are:
CPU dataflow, describing individual components.
LECTURE 18:
August
20, 2002,
CHAPTER 10, Ref. 1: HOMEWORK#10: Part b Will be
Emailed
[Due:
Midnight, August 31, 2002];
Topics are:
Controller, Bussing, Complete the description of V8 URISC.
LECTURE 19:
August 22, 2002,
CHAPTER 12, Ref. 1: HOMEWORK#11: Part c Will be
Emailed [Due:
Midnight, August 31, 2002];
Topics are: Hardware
Software interface. Using the cross assembler.
LECTURE 20:
August 27, 2002,
CHAPTER 12, Ref. 1: HOMEWORK: none.
Topics are: Overflow absorber, Special VHDL
modeling shcemes.
FNAL EXAM: Last
week of August, 2002,
CHAPTERS 1 through 9, and CPU modeling. |
