This 3-day Verilog training course focuses on Verilog Hardware description language from a design point of view.  We will start with presentation of basic constructs and elements of Verilog through use of simple examples. By use of point-examples constructs of the language and their applications will be discussed. After presentation of this introductory material, the course continues with top-down design with Verilog. Complete examples that include bussing and hard-wired controllers will be presented. We will demonstrate the use of a commercial Verilog simulator and students will use this tool in hands-on sessions that follow the lectures.  This 3-day course also covers Verilog for synthesis of digital systems. We begin with presenting point-examples illustrating various constructs of Verilog and how they synthesize to hardware. We will then present a complete digital system and describe it in Verilog for synthesis into simulatable library components. Using a commercial synthesis tool, an online demonstration shows steps that are involved in synthesizing with Verilog.

	General concepts of Verilog and its primitives
	Verilog in a design based on library components
	Behavioral Verilog models for general-purpose components
	Design of large-scale systems by top-down partitioning
	Data components and bus structures in Verilog
	Verilog for description of complex controller circuits
	Use of a commercial simulation software
	Verilog for partitioning a design and synthesizing each part
	Verilog descriptions for synthesis
	Design and synthesis of complex hardware structures
	Use a commercial synthesis tool

"Verilog Digital System Design,” Zainalabedin Navabi, McGraw-Hill Publishing, New York, 1999, ISBN: 0070471649. 

The material covered in this course is covered in this 1999 book from McGraw-Hill.  In addition to the lecture notes, this book will be used as reference.

  A set of 300 slides will be presented in this 3-day course.  Copies of slides will be provided for the participants.

In the first day of the lectures, basic concepts of Verilog and component descriptions will be presented.  Day 2 concentrates on design partitioning and top-down design and simulation.  In the third day, synthesis concepts and use of a synthesis tools in digital system design will be discussed.  The first four hours of every day of will be devoted to lectures.

Use of a commercial simulation tool and a Verilog synthesis tool will be demonstrated in the lectures.  There will be three hands-on sessions that follow the lectures.  In these 3-hour sessions the participants will use simulation and synthesis tools to design several example circuits.  In the first session, participants will learn to describe small components and perform component level simulation.  In day 2, the hands-on session will concentrate on development of a complete system by wiring individual components and performing complete simulations.  Day 3 of hand-on sessions will focus on simulation of synthesis of a complete example.

is an adjunct professor of electrical and computer engineering at Northeastern University. Dr. Navabi is the author of the textbook, VHDL: Analysis and Modeling of Digital Systems, 1993, 1998 McGraw-Hill, and the 1999 book, Verilog Digital System Design. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages (HDL). He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL courses at Northeastern University in 1989. Since then he has conducted many short courses and tutorials on this subject in the United States and abroad. In addition to being a professor, he is also a consultant to CAE companies. Dr. Navabi received his Ph.D. from the University of Arizona in 1981. He is a senior member of IEEE, and a member of IEEE Computer Society, ACM, and ASEE.

 A cut-down version of a Verilog simulation tool is available on the CD that is accompanied with the book and can be used by class participants.  A copy of the full version of this software will also be available for the duration of this course.  Also, arrangements have been made with a commercial synthesis vendor for providing 2 full versions of their software for the duration of this course.   

 For the complete 3-day course the cost to company will be $0000.00.  This is based on $0000.00 per day that includes preparation of the course material, presentation of lectures and conducting hands-on sessions.  This will include 10 sets of copyrighted lecture material that cover the complete 3-day course.  The company is expected to provide the Verilog book that is used as reference for course participants.

The best way to reach me is by sending email to

Phone, fax and message numbers are

	Hardware description languages, evolution of Verilog
	Basic language concepts
	Modules, ports, declarations, assignments
	Using continuous assignments, and alternatives
	Use of always and initial statements for behavioral descriptions
	Timing, scheduling, concurrency, procedural bodies
	Basic logic units, primitives, and flip-flops
	Clocking and clock specification
	Comparators, adders, and complex logic units
	Registers, Counters, and sequential units
	Online demonstration of Verilog simulation software
	Developing behavioral descriptions from word descriptions
	Top-Down recursive partitioning concepts
	Behavioral descriptions for typical parts library components
	Bottom-up wiring
	Developing test benches
	RTL descriptions and necessary components
	State machine descriptions and controllers
	Bussing structures and specification
	High-level behavioral constructs
	Describing a sequential shift-and-add multiplier
	Bi-directional and uni-directional bussing and other datapath components
	One-hot controller description and datapath-control wiring
	Test bench development using external files
	Online demonstration of Verilog simulation of a hierarchical design
	Behavioral, RTL, and logic synthesis
	Basic components of RTL and structural synthesis
	Logic unit synthesis and corresponding hardware
	Combinational circuit and bus synthesis styles
	Register synthesis
	Synthesizing counters and other functional registers
	State machine synthesis with set and resetting
	Synthesis coding of a complete example
	Synthesis style and required packages
	General layout, registers, clocking, sequencing
	Behavioral coding
	Online demonstration of Verilog synthesis of a behavioral design

 An overview of the standard Verilog hardware description language will be presented and a description of hardware at various levels of abstraction will be illustrated in this course. During the introduction, we will discuss the general concepts of Hardware Description Languages, design environments, the evolution of Verilog, and levels of abstraction in Verilog. This course gives a presentation of several examples of the structural, data flow, and behavioral levels of abstraction. The examples will be used to illustrate the concepts of the language and, during the presentation of these examples, syntax and semantics of Verilog constructs that are used will be discussed. Modeling styles for gates, logical structures, and state machines will be presented. We will then continue by presenting design methodologies based on the Verilog HDL. Participants will be shown how Verilog can be used in top-down partitioning of a large design into smaller subcomponents, simulating and testing individual subcomponents, and bottom-up wiring of subcomponents for the formation of a complete design. Describing controllers, busses, register units and interconnection of these components will be shown. An example, which includes several bi-directional busses, shifters, logic units, registers, IO lines, and a complete controller, will be used in this presentation.   After complete presentation of Verilog for description and simulation of digital systems, the course will get into presentation of synthesis concepts.  In this part the course shows how Verilog is used in a design environment for description and synthesis of complex hardware structures. We will start with a presentation of synthesis concepts and synthesis at various levels of abstraction. We will then show how combinational circuits can be described in Verilog for full compatibility with existing commercial synthesis tools.  Next, synthesis styles for sequential circuits including controllers and functional registers will be presented.  Small independent and complete examples will be presented, each to signify a certain synthesizable coding style and its corresponding hardware.  Once ground rules for synthesis have been presented, we will synthesize a design that contains, a controller, several busses and register structures. We will start with a word description of this example and develop a behavioral Verilog description for it.  After performing top-level simulation and verifying the operation of the behavioral description, we will show steps required for synthesis of this example. This will demonstrate how a synthesizable model of a system can be used as input to a synthesis tool for obtaining a complete netlist or FPGA mapping of the complete design. The course includes hands-on sessions for use of commercial simulation and synthesis tools.