"VHDL: Analysis and Modeling of Digital Systems," Zainalabedin Navabi, McGraw-Hill, New York, 2^nd ed. 1998.

"IEEE Standard VHDL Language Reference Manual", IEEE Inc., 1987, New York, NY.

"IEEE Standard VHDL Language Reference Manual", IEEE Inc., 1993, New York, NY.

 Lectures will closely follow the text book.  A 350 page handout will also be provided.  This handout consists of copies of the transparency slides and runs parallel with the text book.  A set of laboratory assignments and their solutions will also be handed out.

 Total number of hours for this training is 30 hours of lecture time and 15 hours of laboratory assistance.  After each lecture, and before the next, a 1½ hour help period (laboratory assistance) will be set up to help class participants with assigned exercises.  The complete training can be done in a 5-week period with two lectures per week, or in a 10-week period with one lecture per week. 

      1)      Basics, Timing, Sequentiality and Concurrency.  Chapters 1,2, 3.

2)      Structural Specification of Hardware.  Chapter 4.

3)      Design Parameterization and Configuration.  Chapter 5.

4)      High Level Language Utilities, Type Declarations.  Chapter 6.

5)      Dataflow Descriptions, Buses, Control.  Chapter 7.

6)      Behavioral descriptions, Process Statements.  Chapter 8.

7)      System Design, A Complete Example.  Chapter 8 & A Tutorial Paper.

8)      Advanced Topics, Standards, Synthesis Principles.  Lecture Notes.

9)      Synthesizability, VHDL for Synthesis.  Lecture Notes.

10)  Logic and Register Synthesis, CPU Modeling for Synthesis.  Chapter 9 & Lecture Notes.

DAY 1 LECTURE:  Design Steps, Simulation and Synthesis, VHDL Evolution, Writing simple component descriptions, VHDL Operators, Objects, Scheduling, Sequentiality and Concurrency, Timing of Events.  (Chapters 1,2, 3 of the Text)

DAY 1 LABORATORY:  Starting with a VHDL simulator, Study of timing, Simulating simple gates.

DAY 2 LECTURE:  Ports and Interface Specification, Specification of System Architecture, Functions and procedures, Wiring of Subcomponents, Using Boolean Expressions for Submodules, Iterative Structures, Binding Alternatives, Test Bench Specification.  (Chapter 4 of the Text).

DAY 2 LABORATORY:  Generating and simulating an iterative design.  Demonstrating binding techniques.

DAY 3 LECTURE:  MSI Parts Configuration, Using VHDL Packages, Packaging Parts and Utilities, Parameterizing Design Variables, Configuration of Design Entities, Design Libraries.  (Chapter 5 of the Text).

DAY 3 LABORATORY:  Describing an adder with iterative constructs, Using timing parameters, Configuring and testing the adder circuit.

DAY 4 LECTURE: Type Declarations, Basic File IO, Type Dependent logical Operations, High Level Hardware Oriented Constructs, Clock Edge Detection, Timing Checks.  (Chapter 6 of the Text).

DAY 4 LABORATORY: Building a general purpose shift-register, Using timing parameters, Setup and Hold time checks, Reading test vectors from a file.

DAY 5 LECTURE: Flip Flops, Signal Assignments, Dataflow Register Modeling, Bus Specification, Block Statements, Control Statements, State Machine Modeling, General Dataflow Description.  (Chapter 7 of the Text).

DAY 5 LABORATORY: Design and simulation of a state machine, Bus and Register data transfer.

DAY 6 LECTURE: Concurrency of Processes, Sequential High Level Constructs, Text IO, Handshaking Processes, Timing Control Statements and Assertions, High Level State Machine Modeling.  (Chapter 8 of the Text).

DAY 6 LABORATORY: Design and simulation of an asynchronous serial receiver/transmitter,  Serial to parallel and parallel to serial converters.

DAY 7 LECTURE: Report Generation, A Complete Example, MSI Parts, Data Control Partitioning, MSI Based Design, Using State Machines for Controllers, Shift-and-ADD Multiplier Design.  (Chapter 8 of Text, and A 40 page Tutorial will be provided).

DAY 7 LABORATORY: Design and simulation of an Adding machine, Using separate data and control parts.

DAY 8 LECTURE: Standard IEEE 1164 Nine Value Logic Value System, VHDL 93 Timing and New Features, Special Modeling Techniques, General Topics in Using VHDL for Synthesis.  (Lecture notes will be provided).

DAY 8 LABORATORY: Enhancing the Adding machine of Laboratory 7 for text IO, Rewriting the Adding machine for synthesis.

DAY 9 LECTURE: VHDL related synthesis issues subset will be presented, Behavioral versus Dataflow synthesis will be discussed and examples presented. ( Lecture notes will be provided).

DAY 9 LABORATORY: Component synthesis.  Generating hardware for small components and simulating pre and post synthesis VHDL code.

DAY 10 LECTURE: Logic and Register synthesis.  Styles for combinational and sequential circuit synthesis.  Developing a synthesis VHDL behavioral code for a small CPU.  ( Lecture notes will be provided).

DAY 10 LABORATORY: State machines, logic units and functional registers will be synthesized.  A complete top-down design, simulation and synthesis will be done.

It is best if the laboratory assignments are compiled and tested with a VHDL simulation software.  For this purpose several copies of a VHDL simulator is needed.  Loaner copies of the software will be provided for use during the term of the training. 

The main text (ISBN# 0-07-046472-3) is available and may be purchased from McGraw-Hill Publishing Inc.  The book can be ordered from McGraw-Hill ordering department, 1-800-338-3987.  In addition to the main text copies of lecture slides (500 pages) covering all the lectures will be provided. 

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