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Prof. Yong-Bin Kim was born in Seoul, South Korea. Prof. Kim received the B.S. degree in Electronic Engineering from Sogang University in Seoul, South Korea, the M.S. degree and PH.D both in Computer Engineering from New Jersey Institute of Technology and Colorado State University, respectively.

From 1982 to 1987, Dr. Kim was with Electronics and Telecommunications Research Institute in South Korea as a Member of technical Staff. From 1990 to 1993 he was with Intel Corp. as a Senior Design Engineer, and involved in micro-controller chip design and Intel P6 microprocessor chip design. From 1993 to 1996 he was with Hewlett Packard Co., Fort Collins, Colorado as a Member of Technical Staff, and involved in HP PA-8000 RISC microprocessor chip design. From 1996 to 1998 he was with Sun Microsystems, Palo Alto, California as an individual contributor, and involved in 1.5GHz Ultra Sparc5 CPU chip design. From 1998 to 2000, he was an assistant professor in the Dept. of Electrical Engineering of University of Utah. He is currently a Professor in the Department of Electrical and Computer Engineering at Northeastern University. His research focuses on high speed low power VLSI circuit design and methodology.


  • PhD, Colorado State University, 1996. Joined Northeastern in 2000.

Research & Scholarship Interests

Integrated circuit design and for nanoelectronics and nano technology, high speed system integration for signal processing and communication applications, bio-chip and bio-sensor interface circuit design, electronic neuron circuit design, low power adaptive robot controller circuit design; high performance and low power vlsI design, system-on-chip (soc), and Physical VLSI CAD
Affiliated With

Department Research Areas

College Research Initiatives

Selected Publications

  • G. Jeon, Y.-B. Kim, A 4Gb/s Half-Rate DFE with Switched-Cap and IIR Summation for Data Correction, IEEE International Symposium on Circuits and Systems, Baltimore, MD, 2017, 2392-2395
  • G. Jeon, Y.-B. Kim, Switched Capacitor and Infinite Impulse Response Summation for a Quad-Rate DFE 4Gb/s Data Rate, ACM GLSVLSI Conference, Banff, Alberta, Canada, 2017, 439-442
  • H. Zhu, W. Yang, G. Engel, Y.-B. Kim, A Two-Parameter Calibration Technique Tracking Temperature Variations for Current Source Miamatch in DACs, IEEE Transactions on Circuits and Systems II, 64(4), 2017, 387-391
  • W. Wei, K. Namba, F. Lombardi, Y.-B. Kim, A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories, IEEE Transactions on Computers, 65(3), 2016, 781-790
  • Y. Choi, Y.-B. Kim, A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface Between DRAM and AP/SoC, Association for Computing Machinery GLSVLSI Conference, 2016, 215-219
  • H. Zhu, R. Kapusta, Y.-B. Kim, Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier, IEEE Transactions on Circuits and Systems 1(TCAS1), 62(7), 2015, 1707-1715
  • I. Jung, Y.-B. Kim, A 12-bit 32MS/s SAR ADC Using Built-In Self Calibration Technique to Minimize Capacitor Mismatch, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems(DFT), August 3-6, Amsterdam, Netherlands, 2014, 275-279
See Google Scholar Profile for all publications »

Related News

September 12, 2018

ECE Associate Professor Marvin Onabajo and Professor Yong-Bin Kim were awarded a patent for creating a "method to use on-chip temperature sensors for detection of Trojan circuits". Abstract...

June 12, 2018

ECE Professor Yong-Bin Kim was awarded a patent for creating an "Impedance calibration device for semiconductor device".

October 31, 2016

ECE Professor Yong-Bin Kim and two PhD students were given the Best Paper Award from the 2016 International SoC Design Conference in Jeju, Korea. The title of the awarded paper is “Current Mode...

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