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The Security of Accelerators

August 16, 2016

ECE professor David Kaeli and associate professor Yunsi Fei were awarded a $450K grant from NSF and SRC for "Side-Channel Analysis and Resiliency Targeting Accelerators".

Abstract Source: NSF

Today's computing systems are becoming increasingly heterogeneous, providing new levels of computational horsepower and power efficiency. Hardware accelerators are a key element in this trend, allowing compute-oriented code to be offloaded to specialized hardware. Accelerators are starting to be used for security services, where high-volume data is encrypted to ensure integrity/confidentiality. However, the security of accelerators has only just begun to receive attention. Issues such as information leakage through side channels have not been addressed. Secure data will continue to grow in importance as we enter into the era of the Internet-of-Things (IoT). This project addresses national security needs, helping individuals, companies and governments to protect their data.

This project develops new knowledge of the attack surface of accelerator devices that are becoming attractive platforms for encryption acceleration. A new class of resiliency approaches are developed to guard sensitive data and reduce the attack surface. The project evaluates side-channel attack vulnerability on a range of systems, including discrete GPUs, integrated APUs (devices with the CPU and GPU sharing memory), and other classes of accelerators. The 3 classes of attacks include: 1) timing attacks, 2) power analysis attacks and 3) electromagnetic emanation attacks. Three resiliency mechanisms are studied: 1) software obfuscation, 2) compiler-assisted modifications to address power/EM leakage, and 3) hardware techniques that add significant timing noise. The project develops tutorials on reliability issues present in accelerator devices. The project provides multiple opportunities for undergraduates from under-represented groups to engage in security-related research.