Adder16: A 16-bit adder with pass mode that passes its input1
to its output. This is used for address
calculations in V8uRISC.
-----------------------------------------------------------------------
-- 16-bit adder
-----------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
ENTITY adder16 IS
PORT (input1 : IN std_logic_vector(15 DOWNTO 0) ;
input2 : IN std_logic_vector(15 DOWNTO 0) ;
output : OUT
std_logic_vector(15 DOWNTO 0) ;
pass : IN
std_logic
) ;
END adder16 ;
ARCHITECTURE adder OF adder16 IS
BEGIN
PROCESS(input1, input2,
pass)
BEGIN
IF (pass = '1') THEN
output <= input1
;
ELSE
output <= input1
+ input2 ;
END IF ;
END PROCESS ;
END adder ;
ALUPACK: An eight bit ALU with arithmetic, shift and
logical operations. A package used by
the ALU has all the ALU operation codes and a function for flag calculations.
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
--
PACKAGE alu_pack IS
CONSTANT ALUINC : std_logic_vector(3 DOWNTO 0) :=
"0000" ;
CONSTANT ALUADD : std_logic_vector(3 DOWNTO 0) :=
"0001" ;
CONSTANT ALUADDC :
std_logic_vector(3 DOWNTO 0) := "0010" ;
CONSTANT ALUDEC : std_logic_vector(3 DOWNTO 0) :=
"0011" ;
CONSTANT ALUSBC : std_logic_vector(3 DOWNTO 0) :=
"0100" ;
CONSTANT ALUCMP : std_logic_vector(3 DOWNTO 0) := "0101"
;
CONSTANT ALUUPP1 :
std_logic_vector(3 DOWNTO 0) := "0110" ;
CONSTANT ALUORR : std_logic_vector(3 DOWNTO 0) :=
"0111" ;
CONSTANT ALUANDD :
std_logic_vector(3 DOWNTO 0) := "1000" ;
CONSTANT ALUXORR :
std_logic_vector(3 DOWNTO 0) := "1001" ;
CONSTANT ALUROLL :
std_logic_vector(3 DOWNTO 0) := "1010" ;
CONSTANT ALURORR :
std_logic_vector(3 DOWNTO 0) := "1011" ;
CONSTANT ALUBTT : std_logic_vector(3 DOWNTO 0) :=
"1100" ;
CONSTANT ALULD : std_logic_vector(3 DOWNTO 0) :=
"1101" ;
CONSTANT ALUUPP2 :
std_logic_vector(3 DOWNTO 0) := "1110" ;
CONSTANT ALUINT : std_logic_vector(3 DOWNTO 0) :=
"1111" ;
FUNCTION
flags210(result : IN std_logic_vector(8 DOWNTO 0))
RETURN
std_logic_vector ; -- 210:NCZ
END alu_pack ;
--
PACKAGE BODY alu_pack IS
FUNCTION
flags210(result : IN std_logic_vector(8 DOWNTO 0))
RETURN std_logic_vector IS
VARIABLE flags :
std_logic_vector(2 DOWNTO 0) ;
BEGIN
IF (result(7 DOWNTO
0) = "00000000") THEN
flags(0) := '1' ;
ELSE
flags(0) := '0' ;
END IF ;
flags(1) := result(8)
;
flags(2) := result(7)
;
RETURN flags ;
END flags210 ;
END alu_pack ;
ALU: An eight bit ALU with arithmetic, shift and
logical operations using the ALUPACK package.
All IEEE standard packages are used.
Overloaded operations in IEEE arithmetic packages are used
------------------------------------------------------------------------
-- alu:
--arithmetic operations
-- INC, ADD, ADDC, DEC, SBC, CMP, UPP, SUB
--logical operations
-- ORR, ANDD, XORR, ROL, ROR
--bit and other operations
-- BTT, LD
------------------------------------------------------------------------
LIBRARY IEEE ;
USE
IEEE.std_logic_1164.ALL ;
USE
IEEE.std_logic_unsigned.ALL ;
USE WORK.alu_pack.ALL ;
ENTITY alu IS
PORT (result : OUT std_logic_vector(7 DOWNTO 0) ;
flagout : OUT
std_logic_vector(3 DOWNTO 0) ;
input1 : IN
std_logic_vector(7 DOWNTO 0) ;
input2 : IN
std_logic_vector(7 DOWNTO 0) ;
flagin
: IN std_logic_vector(3 DOWNTO
0) ;
alucode : IN std_logic_vector(3 DOWNTO 0) ;
num : IN
std_logic_vector(2 DOWNTO 0) ;
rst : IN
std_logic
) ;
END alu ;
--
ARCHITECTURE alu OF alu IS
BEGIN
PROCESS(input1, input2,
alucode, flagin, num, rst)
VARIABLE temp :
std_logic_vector(8 DOWNTO 0) ;
BEGIN
IF (rst = '1') THEN
flagout <=
(OTHERS => '0') ; -- 210:NCZ
temp := (OTHERS => '0') ;
ELSE
flagout <=
flagin ; -- Default is unchanged
CASE alucode IS
WHEN ALUINC =>
temp := ('0' & input1) + 1 ;
flagout(2
DOWNTO 0) <= flags210(temp) ;
WHEN ALUADD =>
temp := ('0' & input1) + input2
;
flagout(2
DOWNTO 0) <= flags210(temp) ;
WHEN ALUADDC
=>
temp := ('0' & input1) + input2
+ flagin(1) ;
flagout(2
DOWNTO 0) <= flags210(temp) ;
WHEN ALUDEC =>
temp := ('0' & input1) - 1 ;
flagout(2
DOWNTO 0) <= flags210(temp) ;
WHEN ALUSBC =>
temp := ('0' & input2) - input1
- flagin(1) ;
flagout(2
DOWNTO 0) <= flags210(temp) ;
WHEN ALUCMP =>
temp := ('0' & input2) - input1 ;
flagout(2
DOWNTO 0) <= flags210(temp) ;
WHEN ALUUPP1
=>
temp := ('0' & input1) + 1 ;
flagout(1)
<= flags210(temp)(1) ;
WHEN ALUUPP2
=>
temp := ('0' & input2) + flagin (1) ;
flagout(1)
<= flags210(temp)(1) ;
WHEN ALUORR =>
temp := '0' & (input1 OR
input2) ;
flagout(2
DOWNTO 0) <= flags210(temp)(2) & flagin(1) & flags210(temp)(0) ;
WHEN ALUANDD
=>
temp := '0' & (input1 AND input2) ;
flagout(2
DOWNTO 0) <= flags210(temp)(2) & flagin(1) & flags210(temp)(0) ;
WHEN ALUXORR
=>
temp := '0' & (input1 XOR
input2) ;
flagout(2
DOWNTO 0) <= flags210(temp)(2) & flagin(1) & flags210(temp)(0) ;
WHEN ALUROLL
=>
temp := input1 & flagin(1) ;
flagout(2
DOWNTO 0) <= flags210(temp) ;
WHEN ALURORR
=>
temp :=
input1(0) & flagin(1) & input1(7 DOWNTO 1) ;
flagout(2
DOWNTO 0) <= flags210(temp) ;
WHEN ALUBTT =>
flagout(0)
<= NOT input1(conv_integer(num)) ;
WHEN ALULD =>
temp := '0'
& input1 ;
flagout(2
DOWNTO 0) <= flags210(temp)(2) & flagin(1) & flags210(temp)(0) ;
WHEN ALUINT =>
flagout(3)
<= '1';
WHEN OTHERS =>
temp := (OTHERS => '0') ;
flagout(2
DOWNTO 0) <= "000" ;
END CASE ;
END IF ;
result <= temp(7
DOWNTO 0) ;
END PROCESS ;
END alu ;
BITCSC: An eight
bit combinational logic that puts a 1 or 0 on its selected output. Also, the value of a selected bit of the
input appears on a one-bit output of this circuit. IEEE packages and arithmetic conversion functions are used here.
------------------------------------------------------------------------
-- 8-bit select, set, clear
------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
--
ENTITY bitcsc IS
PORT (din : IN
std_logic_vector(7 DOWNTO 0) ;
dout : OUT std_logic_vector(7 DOWNTO 0) ;
bz : OUT std_logic ;
num : IN
std_logic_vector(2 DOWNTO 0) ;
sccb : IN
std_logic ;--secclear/~chek
setclearb :
IN std_logic) ;
END bitcsc ;
--
ARCHITECTURE bit OF bitcsc IS
BEGIN
PROCESS (sccb, din,
setclearb, num)
variable bzz:
integer ;
BEGIN
bzz := conv_integer(num) ;
CASE num IS
WHEN "000" =>
bz<= din(0) ;
WHEN "001" =>
bz<= din(1) ;
WHEN "010" =>
bz<= din(2) ;
WHEN "011" =>
bz<= din(3) ;
WHEN "100" =>
bz<= din(4) ;
WHEN "101" =>
bz<= din(5) ;
WHEN "110" =>
bz<= din(6) ;
WHEN "111" =>
bz<= din(7) ;
WHEN others =>
bz<= '0' ;
end CASE ;
dout <= din ;
IF (sccb = '1') THEN
dout(bzz) <=
setclearb ;
END IF ;
END PROCESS ;
END bit ;
DATAREG: A
16-bit register that shares its 8-bit input between its two register
halves. Each register half is
controlled independently using active high enable inputs. IEEE packages are used here.
------------------------------------------------------------------------
-- 16bit data register
------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
ENTITY datareg IS
PORT (din : IN
std_logic_vector(7 DOWNTO 0) ;
dout : OUT
std_logic_vector(15 DOWNTO 0) ;
clk : IN
std_logic ;
enh :
IN std_logic ;
enl : IN
std_logic
) ;
END datareg ;
--
ARCHITECTURE dreg OF datareg IS
BEGIN
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk
= '1') THEN
IF (enh = '1') THEN
dout(15 DOWNTO 8)
<= din ;
END IF ;
IF (enl = '1') THEN
dout(7 DOWNTO
0) <= din ;
END IF ;
END IF ;
END PROCESS ;
END dreg ;
Incrementer: A 3-bit
combinational incrementer. Overloaded
IEEE functions are used.
------------------------------------------------------------------------
-- 3-bit incrementer
-----------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_arith.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
ENTITY incrementer IS
PORT ( input : IN
std_logic_vector (2 DOWNTO 0) ;
output : OUT
std_logic_vector (2 DOWNTO 0)) ;
END incrementer ;
ARCHITECTURE increment
OF incrementer IS
BEGIN
output <= input + 1 ;
END increment ;
IRREG: An
8-bit register with separate 3-bit and 5-bit outputs. The register has synchronous enable input. IEEE packages are used here.
------------------------------------------------------------------------
-- 8-bit instruction register
------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_arith.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
--
ENTITY irreg IS
PORT (din : IN std_logic_vector (7 DOWNTO 0) ;
num : OUT std_logic_vector (2 DOWNTO 0) ;
op : OUT std_logic_vector (4 DOWNTO 0) ;
clk : IN std_logic ;
en : IN std_logic) ;
END irreg ;
ARCHITECTURE irreg8 OF irreg IS
BEGIN
PROCESS (clk, en, din)
BEGIN
IF (clk'EVENT AND clk =
'1') THEN
IF en = '1' THEN
op <= din (7 DOWNTO 3) ;
num <= din (2 DOWNTO 0) ;
END IF ;
END IF ;
END PROCESS ;
END irreg8 ;
PSRREG: An
8-bit register separated into two 4-bit parts.
Each part has its own clock enabling.
The reset and the clock inputs are shared. IEEE packages are used.
------------------------------------------------------------------------
-- psr register
------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
ENTITY psrreg IS
PORT (douth : OUT
std_logic_vector(3 DOWNTO 0) ;
doutl : OUT
std_logic_vector(3 DOWNTO 0) ;
dinh : IN
std_logic_vector(3 DOWNTO 0) ;
dinl : IN
std_logic_vector(3 DOWNTO 0) ;
clk : IN
std_logic ;
enh : IN
std_logic ;
enl : IN
std_logic ;
rst : IN
std_logic) ;
END psrreg ;
ARCHITECTURE psr OF psrreg IS
BEGIN
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk
= '1') THEN
IF (enh = '1') THEN
IF (rst = '1')
THEN
douth <=
(OTHERS => '0') ;
ELSE
douth <= dinh ;
END IF ;
END IF ;
IF (enl = '1') THEN
IF (rst = '1')
THEN
doutl <=
(OTHERS => '0') ;
ELSE
doutl <=
dinl ;
END IF ;
END IF ;
END IF ;
END PROCESS ;
END psr ;
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY encoder IS PORT (int : in std_logic_vector (7 downto 0);
adr : out
std_logic_vector (7 downto 0)) ;
END encoder ;
--
ARCHITECTURE behavioral OF encoder IS
BEGIN
adr <= int (6 DOWNTO
0) & '0';
END behavioral ;
REG16 (PC): A 16-bit
register with synchronous enable and reset inputs. IEEE packages are used here.
------------------------------------------------------------------------
-- 16bit register (PC)
------------------------------------------------------------------------
LIBRARY IEEE ;
USE
IEEE.std_logic_1164.ALL ;
ENTITY program_counter IS
PORT (din : IN
std_logic_vector(15 DOWNTO 0) ;
dout : OUT
std_logic_vector(15 DOWNTO 0) ;
clk : IN
std_logic ;
rst : IN
std_logic ;
en : IN
std_logic) ;
END program_counter ;
ARCHITECTURE behavioral OF program_counter IS
BEGIN
PROCESS (clk, rst, en,
din)
BEGIN
IF (clk'EVENT AND clk
= '1') THEN
IF (en = '1') THEN
IF (rst = '1')
THEN
dout <= (OTHERS => '0') ;
ELSE
dout <= din
;
END IF ;
END IF ;
END IF ;
END PROCESS ;
END behavioral ;
REGFILE: A
two-output register file with 8 8-bit registers. Data from two selected registers are always available on the two
outputs of the register. Input data
into the register file is clocked into a selected register on the positive
clock edge. The regwrite input enables clocked writes into the register file. All select inputs are 3 bits wide, accessing
one of the 8 registers of the file.
IEEE packages including arithmetic and overloaded functions are used
here.
------------------------------------------------------------------------
-- Eight-bit registerfile
------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
ENTITY regfile IS
PORT (read_reg_num1 :
IN std_logic_vector(2 DOWNTO 0) ;
read_reg_num2 :
IN std_logic_vector(2 DOWNTO 0) ;
write_reg_num : IN std_logic_vector(2 DOWNTO 0) ;
writedata : IN
std_logic_vector(7 DOWNTO 0) ;
regwrite : IN
std_logic ;
regread : IN
std_logic ;
rst : IN std_logic ;
clk : IN std_logic ;
regout1 : OUT std_logic_vector(7 DOWNTO 0) ;
regout2 : OUT std_logic_vector(7 DOWNTO 0) ) ;
END regfile ;
ARCHITECTURE behavioral OF regfile IS
TYPE registerbank IS
array(7 DOWNTO 0)OF std_logic_vector(7 DOWNTO 0) ;
SIGNAL regbank :
registerbank ;
BEGIN
regout1 <= regbank
(conv_integer (read_reg_num1)) ;
regout2 <= regbank
(conv_integer (read_reg_num2)) ;
PROCESS(clk)
BEGIN
IF (clk = '1' AND
clk'EVENT) THEN
IF (rst = '1') THEN
regbank(7 DOWNTO
0) <= (OTHERS => (OTHERS => '0')) ;
ELSIF (regwrite =
'1') THEN
regbank
(conv_integer(std_logic_vector(write_reg_num))) <= writedata ;
END IF ;
END IF ;
END PROCESS ;
END behavioral ;
SPREG: An eight
bit count up / count down register with synchronous enable and reset
inputs. The incdecb input controls the count up and down modes. IEEE packages including overloaded
arithmetic functions are used.
------------------------------------------------------------------------
-- 8-bit stack pointer register
------------------------------------------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
ENTITY spreg IS
PORT (dout : OUT std_logic_vector(7 DOWNTO 0) ;
clk : IN
std_logic ;
en : IN
std_logic ;
incdecb : IN std_logic ;
rst : IN
std_logic) ;
END spreg ;
--
ARCHITECTURE sp OF spreg IS
SIGNAL sdout :
std_logic_vector(dout'RANGE) ;
BEGIN
dout <= sdout ;
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk
= '1') THEN
IF (en = '1') THEN
IF (rst = '1')
THEN
sdout <=
"11001111" ;
ELSIF (incdecb =
'1') THEN
sdout <=
sdout + 1 ;
ELSE
sdout <=
sdout - 1 ;
END IF ;
END IF ;
END IF ;
END PROCESS ;
END sp ;
Controller: A state
machine implementation of the controller.
It uses a case statement to issue various control signals.
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
--
PACKAGE control_pack IS
CONSTANT INC : std_logic_vector(4 DOWNTO 0)
:="00000" ;
CONSTANT ADC : std_logic_vector(4 DOWNTO 0)
:="00001" ;
CONSTANT TX0 : std_logic_vector(4 DOWNTO 0)
:="00010" ;
CONSTANT ORR : std_logic_vector(4 DOWNTO 0)
:="00011" ;
CONSTANT ANDD :
std_logic_vector(4 DOWNTO 0) :="00100" ;
CONSTANT XORR :
std_logic_vector(4 DOWNTO 0) :="00101" ;
CONSTANT ROLL :
std_logic_vector(4 DOWNTO 0) :="00110" ;
CONSTANT RORR :
std_logic_vector(4 DOWNTO 0) :="00111" ;
CONSTANT DEC : std_logic_vector(4 DOWNTO 0)
:="01000" ;
CONSTANT SBC : std_logic_vector(4 DOWNTO 0)
:="01001" ;
CONSTANT ADD : std_logic_vector(4 DOWNTO 0)
:="01010" ;
CONSTANT STP : std_logic_vector(4 DOWNTO 0)
:="01011" ;
CONSTANT BTT : std_logic_vector(4 DOWNTO 0)
:="01100" ;
CONSTANT CLP : std_logic_vector(4 DOWNTO 0)
:="01101" ;
CONSTANT T0X : std_logic_vector(4 DOWNTO 0)
:="01110" ;
CONSTANT CMP : std_logic_vector(4 DOWNTO 0)
:="01111" ;
CONSTANT PSH : std_logic_vector(4 DOWNTO 0)
:="10000" ;
CONSTANT POP : std_logic_vector(4 DOWNTO 0)
:="10001" ;
CONSTANT BR0 : std_logic_vector(4 DOWNTO 0)
:="10010" ;
CONSTANT BR1 : std_logic_vector(4 DOWNTO 0)
:="10011" ;
CONSTANT USR : std_logic_vector(4 DOWNTO 0)
:="10100" ;
CONSTANT INT : std_logic_vector(4 DOWNTO 0)
:="10101" ;
CONSTANT USR2 :
std_logic_vector(4 DOWNTO 0) :="10110" ;
CONSTANT JMP : std_logic_vector(4 DOWNTO 0)
:="10111" ;
CONSTANT UPP : std_logic_vector(4 DOWNTO 0)
:="11000" ;
CONSTANT STA : std_logic_vector(4 DOWNTO 0)
:="11001" ;
CONSTANT STXX :
std_logic_vector(4 DOWNTO 0) :="11010" ;
CONSTANT STO : std_logic_vector(4 DOWNTO 0)
:="11011" ;
CONSTANT LDI : std_logic_vector(4 DOWNTO 0)
:="11100" ;
CONSTANT LDA : std_logic_vector(4 DOWNTO 0)
:="11101" ;
CONSTANT LDX : std_logic_vector(4 DOWNTO 0)
:="11110" ;
CONSTANT LDO : std_logic_vector(4 DOWNTO 0)
:="11111" ;
END control_pack ;
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE WORK.alu_pack.ALL ;
USE WORK.control_pack.ALL ;
ENTITY controller IS PORT
(opcode : IN std_logic_vector (4 DOWNTO 0) ;
clk : IN std_logic ;
rst : IN std_logic ;
bitcscz : IN std_logic ;
num : IN
std_logic_vector (2 DOWNTO 0) ;
h_int : IN std_logic_vector (7 DOWNTO 0) ;
enpc : OUT std_logic
;
rstpc : OUT std_logic
;
ensp : OUT std_logic
;
rstsp : OUT std_logic ;
incdecbsp : OUT std_logic ;
passadder : OUT std_logic ;
alucode : OUT std_logic_vector (3 DOWNTO 0) ;
rstalu : OUT std_logic ;
sccbbitcsc : OUT std_logic ;
setclearbbitcsc : OUT std_logic ;
enhdatareg : OUT std_logic ;
enldatareg : OUT std_logic ;
enirreg : OUT std_logic ;
memwrite : OUT std_logic ;
memread : OUT std_logic ;
memrst : OUT std_logic ;
memen : OUT std_logic
;
enhpsr : OUT std_logic ;
enlpsr : OUT std_logic ;
rstpsr : OUT std_logic ;
regread : OUT std_logic ;
regwrite : OUT std_logic ;
regfilerst : OUT std_logic ;
sp_on_addressbus : OUT std_logic ;
oadder_on_addressbus
: OUT std_logic ;
opc_on_addressbus : OUT std_logic ;
regout2regout1_on_addressbus: OUT std_logic ;
odatareg_on_addressbus
: OUT std_logic ;
psr_on_databus : OUT std_logic ;
opch_on_databus : OUT std_logic ;
opcl_on_databus : OUT std_logic ;
ohdatareg_on_databus
: OUT std_logic ;
oldatareg_on_databus
: OUT std_logic ;
regout1_on_databus : OUT std_logic ;
memdataout_on_databus
: OUT std_logic ;
int_adr_on_i1adder : OUT std_logic ;
opc_on_i1adder : OUT std_logic ;
addressbus_on_i1adder
: OUT std_logic ;
odatareg_on_i1adder
: OUT std_logic ;
regout2regout1_on_i1adder
: OUT std_logic ;
oencoder_on_i1adder
: OUT std_logic ;
one_on_i2adder : OUT std_logic ;
oldatareg_on_i2adder
: OUT std_logic ;
oldatareg_signed_on_i2adder
: OUT std_logic ;
databus_on_regfile_write_data
: OUT std_logic ;
result_alu_on_regfile_write_data
: OUT std_logic ;
num_on_regfile_read_reg_num1 :
OUT std_logic ;
zero_on_regfile_read_reg_num1
: OUT std_logic ;
latched_num_on_regfile_read_reg_num1
: OUT std_logic ;
num_plus_on_regfile_read_reg_num2
: OUT std_logic ;
zero_on_regfile_read_reg_num2
: OUT std_logic ;
num_plus_on_regfile_write_reg_num
: OUT std_logic ;
num_on_regfile_write_reg_num
: OUT std_logic ;
latched_num_on_regfile_write_reg_num
: OUT std_logic ;
zero_on_regfile_write_reg_num
: OUT std_logic ;
regout1_on_idatareg
: OUT std_logic ;
databus_on_idatareg
: OUT std_logic ;
regout1_on_i1alu : OUT std_logic ;
databus_on_i1alu : OUT std_logic ;
obitcsc_on_ilpsr : OUT std_logic ;
flagoutalu_on_ilpsr
: OUT std_logic) ;
END controller ;
ARCHITECTURE ctrl OF controller IS
TYPE stateTYPE IS
(fetch,
push, push1, pop1,
br00, br01,
jmp0, jmp1, jmp2,
jsr0, jsr1, jsr2, jsr3, jsr4,
hlt,nop, nop1,
rts0, rts1, rts2,
rti0, rti1, rti2,
brk0, brk1, brk2,brk3,
up0,
sta0,
sta1,sta2,lda0,lda1,lda2,
stx0,ldx0,
sto0,sto1,ldo0,ldo1,
ldi0,
ints0,ints1,ints2,inth0,inth1,inth2,int3,
int4, int5
) ;
SIGNAL state, nstate :
statetype ;
BEGIN
PROCESS (state,
opcode, rst, bitcscz, num, h_int)
BEGIN
-- Set all signals to
their inactive states
enpc <= '0' ;
rstpc <= '0' ;
ensp <= '0' ;
rstsp <= '0' ;
incdecbsp <= '0' ;
passadder <= '0' ;
alucode <=
"0000" ;
rstalu <= '0' ;
sccbbitcsc <= '0' ;
setclearbbitcsc
<= '0' ;
enhdatareg <= '0' ;
enldatareg <= '0' ;
enirreg <= '0' ;
memwrite <= '0' ;
memread <= '0' ;
memen <= '0' ;
enhpsr <= '0' ;
enlpsr <= '0' ;
rstpsr <= '0' ;
regread <= '0' ;
regwrite <= '0' ;
regfilerst <= '0' ;
sp_on_addressbus
<= '0' ;
oadder_on_addressbus <= '0' ;
opc_on_addressbus
<= '0' ;
regout2regout1_on_addressbus
<= '0' ;
odatareg_on_addressbus
<= '0' ;
opch_on_databus
<= '0' ;
opcl_on_databus <= '0' ;
ohdatareg_on_databus
<= '0' ;
oldatareg_on_databus
<= '0' ;
regout1_on_databus
<= '0' ;
memdataout_on_databus
<= '0' ;
opc_on_i1adder <= '0' ;
addressbus_on_i1adder
<= '0' ;
odatareg_on_i1adder
<= '0' ;
regout2regout1_on_i1adder
<= '0' ;
one_on_i2adder <= '0' ;
oldatareg_on_i2adder
<= '0' ;
oldatareg_signed_on_i2adder
<= '0' ;
databus_on_regfile_write_data
<= '0' ;
result_alu_on_regfile_write_data
<= '0' ;
num_on_regfile_read_reg_num1
<= '0' ;
zero_on_regfile_read_reg_num1
<= '0' ;
latched_num_on_regfile_read_reg_num1 <= '0' ;
num_plus_on_regfile_read_reg_num2
<= '0' ;
zero_on_regfile_read_reg_num2
<= '0' ;
num_plus_on_regfile_write_reg_num
<= '0' ;
num_on_regfile_write_reg_num
<= '0' ;
latched_num_on_regfile_write_reg_num <= '0' ;
zero_on_regfile_write_reg_num
<= '0' ;
regout1_on_idatareg
<= '0' ;
databus_on_idatareg <= '0' ;
regout1_on_i1alu
<= '0' ;
databus_on_i1alu
<= '0' ;
obitcsc_on_ilpsr
<= '0' ;
flagoutalu_on_ilpsr
<= '0' ;
-----------------------------
oencoder_on_i1adder <= '0'
;
int_adr_on_i1adder
<= '0' ;
----------------------------------
IF (rst = '1') THEN
enpc <= '1' ;
rstpc <= '1' ;
ensp <= '1' ;
rstsp <= '1' ;
rstalu <= '1' ;
memread <= '1' ;
memen <= '1' ;
enhpsr <= '1' ;
enlpsr <= '1' ;
rstpsr <= '1' ;
enirreg <= '1' ;
regread <= '1' ;
regfilerst <= '1' ;
nstate <= fetch ;
ELSE
CASE state IS
WHEN fetch
=>
enpc <='1' ;
enirreg <='1' ;
memread <='1' ;
memen <='1' ;
regread <='1' ;
opc_on_addressbus <='1' ;
memdataout_on_databus <='1' ;
opc_on_i1adder <='1' ;
one_on_i2adder <='1' ;
IF h_int /=
"00000000" THEN
enpc <= '0' ;
nstate <=
inth0 ;
ELSE
CASE opcode
IS -- part of fetch state
-------------------------------------------------------------------------
WHEN
INC =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
regwrite <= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1
<= '1' ;
num_on_regfile_write_reg_num
<= '1' ;
regout1_on_i1alu <= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus
<= '1' ;
alucode
<= ALUINC ;
nstate <= fetch ;
-------------------------------------------------------------------------
WHEN
ADC =>
-------------------------------------------------------------------------
enlpsr <= '1' ;
regwrite
<= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1
<= '1' ;
zero_on_regfile_read_reg_num2
<= '1' ;
zero_on_regfile_write_reg_num
<= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus <= '1' ;
alucode
<= ALUADDC ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN
TX0 =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
regwrite
<= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1
<= '1' ;
zero_on_regfile_read_reg_num2
<= '1' ;
zero_on_regfile_write_reg_num
<= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus
<= '1' ;
alucode
<=ALULD ;
nstate <= fetch ;
-------------------------------------------------------------------------
WHEN
ORR =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
regwrite <= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1
<= '1' ;
zero_on_regfile_read_reg_num2
<= '1' ;
zero_on_regfile_write_reg_num
<= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus
<= '1' ;
alucode <= ALUORR ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN
ANDD =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
regwrite
<= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1 <= '1' ;
zero_on_regfile_read_reg_num2
<= '1' ;
zero_on_regfile_write_reg_num
<= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr <= '1' ;
opc_on_addressbus
<= '1' ;
alucode
<= ALUANDD ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN
XORR =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
regwrite <= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1
<= '1' ;
zero_on_regfile_read_reg_num2
<= '1' ;
zero_on_regfile_write_reg_num <= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus
<= '1' ;
alucode <= ALUXORR ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN
ROLL =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
regwrite
<= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1 <= '1' ;
num_on_regfile_write_reg_num
<= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus <= '1' ;
alucode
<= ALUROLL ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN RORR =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
regwrite
<= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1
<= '1' ;
num_on_regfile_write_reg_num
<= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus
<= '1' ;
alucode
<= ALURORR ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN
DEC =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
regwrite <= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1
<= '1' ;
num_on_regfile_write_reg_num
<= '1' ;
regout1_on_i1alu <= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus
<= '1' ;
alucode
<= ALUDEC ;
nstate <= fetch ;
-------------------------------------------------------------------------
WHEN
SBC =>
-------------------------------------------------------------------------
enlpsr <= '1' ;
regwrite
<= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1
<= '1' ;
zero_on_regfile_read_reg_num2
<= '1' ;
zero_on_regfile_write_reg_num
<= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus <= '1' ;
alucode
<= ALUSBC ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN
ADD =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
regwrite
<= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_read_reg_num1
<= '1' ;
zero_on_regfile_read_reg_num2
<= '1' ;
zero_on_regfile_write_reg_num
<= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus
<= '1' ;
alucode
<= ALUADD ;
nstate <= fetch ;
-------------------------------------------------------------------------
WHEN
STP =>
-------------------------------------------------------------------------
sccbbitcsc <= '1' ;
setclearbbitcsc <= '1' ;
enhpsr <= '1' ;
enlpsr <= '1' ;
opc_on_addressbus <= '1' ;
obitcsc_on_ilpsr <= '1' ;
nstate <= fetch ;
-------------------------------------------------------------------------
WHEN
BTT =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
zero_on_regfile_read_reg_num1 <= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus
<= '1' ;
alucode <= ALUBTT ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN
CLP =>
-------------------------------------------------------------------------
sccbbitcsc
<= '1' ;
setclearbbitcsc
<= '0' ;--not needed
enhpsr
<= '1' ;
enlpsr <= '1' ;
obitcsc_on_ilpsr
<= '1' ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN
T0X =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
regwrite
<= '1' ;
result_alu_on_regfile_write_data
<= '1' ;
num_on_regfile_write_reg_num <= '1' ;
zero_on_regfile_read_reg_num1
<= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus <= '1' ;
alucode
<= ALULD ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN
CMP =>
-------------------------------------------------------------------------
enlpsr
<= '1' ;
num_on_regfile_read_reg_num1
<= '1' ;
zero_on_regfile_read_reg_num2 <= '1' ;
regout1_on_i1alu
<= '1' ;
flagoutalu_on_ilpsr
<= '1' ;
opc_on_addressbus
<= '1' ;
alucode <= ALUCMP ;
nstate
<= fetch ;
-------------------------------------------------------------------------
WHEN
PSH =>
-------------------------------------------------------------------------
num_on_regfile_read_reg_num1 <= '1' ;
enhdatareg
<= '1' ;
regout1_on_idatareg
<= '1' ;
nstate <=
push ;
-------------------------------------------------------------------------
WHEN
POP =>
-------------------------------------------------------------------------
ensp <= '1' ;
incdecbsp <= '0' ;--not needed
nstate <= pop1 ;
-------------------------------------------------------------------------
WHEN
BR0 =>
-------------------------------------------------------------------------
IF (bitcscz = '0') THEN
nstate <= br00 ;
ELSE
nstate <= nop1 ;
END
IF ;
-------------------------------------------------------------------------
WHEN
BR1 =>
-------------------------------------------------------------------------
IF
(bitcscz = '1') THEN
nstate <= br00 ;
ELSE
nstate <= nop1 ;
END
IF ;
-------------------------------------------------------------------------
WHEN
USR | USR2 =>
-------------------------------------------------------------------------
nstate <= nop ;
-------------------------------------------------------------------------
WHEN
INT =>
-------------------------------------------------------------------------
nstate <= ints0 ;
-------------------------------------------------------------------------
WHEN
JMP =>
CASE
num IS
WHEN "000" => --RSP (reset stack pointer)
ensp <= '1' ;
rstsp <= '1' ;
nstate <= fetch ;
WHEN "001" => --RTS(return
From Subroutine)
ensp <= '1' ;
nstate <= rts0 ;
WHEN "010" => --RTI
(Return From Interrupt)
ensp <= '1' ;
nstate <= rti0 ;
WHEN "011" => --BRK(5 nop operation)
enpc <= '1' ;
nstate <= brk0 ;
WHEN "100"
=>--JMP
nstate <= jmp0 ;
WHEN "111" => -
