RT Level Design and Test

This chapter discusses design and test of complete systems.  Topics discussed in Chapters 4, 5 and 6 are used here to describe systems for synthesis and develop testbenches for these complete systems.  We will show how a design is partitioned into its datapath and controller and how these components are described in Verilog.  In a complex design we will show further partitioning of the datapath of the design into its individual registers, busses, and logic units.  For testing our designs, we show how interactive testing and use of files are utilized for testing actual systems.  The chapter begins with specification and design of a sequential multiplier.  We will then discuss a simple processor to familiarize readers with design methodology that we are promoting for larger systems.  The last section of this chapter uses our design methodology to design, code and test a CPU with a typical architecture.