Overview of the Chapters

            Chap. 1 gives an overview of digital design process and the use of hardware description languages in this process.  Simulation, synthesis, formal verification and assertion verification are discussed in this chapter. 

            Chap. 2 shows various ways hardware components can be described in Verilog.  The purpose of this chapter is to give the reader a general overview of the Verilog language.

            Chap. 3 discusses the complete Verilog language structure.  The focus of the chapter is more on the linguistic issues and not on modeling hardware components.  A general understanding of the language is necessary before it can be used for hardware modeling.  Writing Verilog for describing hardware is discussed in the chapters that follow this chapter.

            Chap. 4 starts with gates and ends with high level Verilog constructs for description of combinational circuits.  Concurrency and timing will be discussed in the examples of this chapter.  Except for specification of timing parameters, codes discussed in this chapter are synthesizable.  A section in this chapter presents rules for writing synthesizable combinational circuits.

            Chap. 5 discusses modeling and description of sequential circuits in Verilog.  The chapter begins with models of memory and shows how they can be specified in Verilog.  Registers, counters, and state machines are discussed in this chapter.  A section in this chapter presents rules for writing synthesizable sequential circuits.

            Chap. 6 is on writing testbenches in Verilog.  The previous two chapters discussed Verilog from a hardware design point of view, and this chapter shows how components described as such can be tested.  We talk about data generation, response analysis, and assertion verification.

            Chap. 7 covers switch level modeling and detailed representation of signals in Verilog.  This material is geared more for those using Verilog as a modeling language and less for designers.  VLSI structures can be described by Verilog constructs discussed here. 

            Chap. 8 shows complete RTL design flow, from problem specification to test.  We show several complete examples that take advantage of material of Chapters 4, 5, and 6 for description, simulation, verification, and synthesis of digital systems.  Examples in this chapter take advantage of text IO facilities of Verilog for storing test data and circuit responses.

            Appendix A shows Verilog keywords.  Appendix B lists commonly used system tasks and briefly describes each task.  Appendix C lists Verilog compiler directives and explains their use.  Appendix D presents the standard IEEE Verilog HDL syntax.  Language constructs terminals and non-terminals are presented here in a formal grammar representation.  Appendix E presents the OVL assertion monitors.  After a brief description of each assertion monitor its parameters and arguments are explained.