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Interaction Between Compilers and Computer Architecture
Research Students:
Murat Bicer
Efe Yardimci
Recent Participants:
Hakan Aydin
Amir Hooshang Hashemi
John Kalamatianos
Suleyman Sair
Svetlana Sokolova
Faculty:
Prof. David Kaeli

Project Summary:
I n past work we explored link-time basic block and procedure mapping techniques to reduce conflict misses in low-associativity instruction caches.

In present work we are studying data structure layout and memory allocation strategies, as well as profile-guided compilation techniques. We are also looking at ways to utilize profile counters during program optimization.

In July 1999 the National Science Foundation provided a grant (CCR-9900615) titled: "Profile-Driven Compile-Time Optimizations Targeting Commodity Desktop Environments."

In September 2000, Mercury Computer provided a grant titled: ``Profile-Guided Optimization Targeting Dataflow Architectures.'' Past support has been provided by Compaq Computer, IBM Corporation and Microsoft Research.

Publications:
  1. `` Welcome to the Opportunities of Binary Translation'' , IEEE Computer Magazine , March 2000, pp. 40-46.

  2. " Profile-guided Tuning of Heap-based Memory Access ", 2nd Workshop on Memory Performance Issues, Goteberg, Sweden, July 2001.

  3. " Microarchitecture-aware Profile-guided Heap Allocation ", submitted to the 2001 IEEE Conference on Parallel Architectures and Compilation Techniques.

  4. `` Analysis of Temporal-based Program Behavior for Improved Instruction Cache Performance'' , IEEE Transactions on Computers , Vol.10, No. 2, February 1999, pp. 168-175.

  5. `` Cache Line Coloring Using Real and Estimated Profiles'' , Digital Technical Journal Special Issue on Tools and Languages , February 1999.

  6. `` Accurate Simulation and Evaluation of Code Reordering,'' , in the Proceedings of the IEEE International Symposium on the Performance Analysis of Systems and Software , Austin, TX, April 2000.

  7. `` Studying the Performance of the FX!32 Binary Translation System,'' , in the Proceedings of the 1st Workshop on Binary Translation , Newport Beach, CA, Oct. 1999.

  8. `` Parameter Value Characterization of Windows NT-based Applications,'' , Workload Characterization: Methodology and Case Studies , IEEE Computer Society, 1999, pp.142-149.

  9. " Temporal-Based Procedure Reordering for Improved Instruction Cache Performance, " Proc. of the 4th International Conference High Performance Computer Architecture , Las Vegas, NV, February 1998, pp. 244-253.

  10. " Efficient Procedure Mapping Using Cache Line Coloring", in the Proceedings of
    SIGPLAN Conference on Programming Language Design and Implementation    , June 1997, pp. 171-182.