Research: Soft Error Related Topics

· Soft Error Rate Estimation and Mitigation of SRAM-Based FPGAs

FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Previous techniques on FPGA SER estimation are based on time-consuming fault injection and simulation methods. In this project, we are developing an analytical approach to estimate the failure rate of designs mapped into FPGAs. We are also developing a high-reliable low-cost mitigation technique to improve the availability of FPGA-based designs.

· Reliability of the Cache Memory Hierarchy

Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this project, we have developed a new method to accurately estimate the reliability of cache memories. We look at the vulnerability of multiple levels of the cache hierarchy to soft errors using a reliability and performance evaluation framework, which has been built upon the Simplescalar simulator. Using this framework, we can report on the detailed vulnerability of data, tag-addresses, and status bits of cache memories.

· System Level Soft Error Rate Estimation

Soft errors due to single event upsets are becoming the main threat for reliability and availability of most of digital systems in near future. Estimation of system-level soft error rate is a key factor to compute dependability parameters of digital circuits and develop appropriate soft error tolerant techniques. In this research project, a systematic approach for estimation of system failure due to soft errors in the components for both combinational and sequential circuits at logic-level is concerned.

Team Members:

· Prof. David Kaeli

· Prof. Mehdi B. Tahoori

· Hossein Asadi

· Vilas Sridharan

Description:

FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Previous techniques on FPGA SER estimation are based on time-consuming fault injection and simulation methods. In this project, we are developing an analytical approach to estimate the failure rate of designs mapped into FPGAs. We are also developing a high-reliable low-cost mitigation technique to improve the availability of FPGA-based designs.

Publications

JN: Journal Paper

CN: Conference Paper

CN	·	H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Reliability Tradeoffs in Design of Cache Memories,” Accepted in the Workshop on Architectural Reliability (WAR-1), held in conjunction with 38th International Symposium on Microarchitecture (MICRO-38), Barcelona, Spain, Dec. 2005.
JN	·	H. Asadi, V. Schridhar, M. B. Tahoori, and D. Kaeli, “Exploring Selective Refetch to Reduce Data Cache Soft-Error Susceptibility,” Under review in the IEEE Transactions on Dependability.
CN	·	H. Asadi and M. B. Tahoori, “Soft Error Modeling and Protection for Sequential Elements”, Proc. of the IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), pp. 463-471, Monterey, CA, Oct. 2005.
CN	·	G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation in Digital Circuits,” Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 2005.
CN	·	G.  Asadi and M. B. Tahoori, “Soft Error Mitigation for SRAM-Based FPGAs,” Proc. of the 23^rd IEEE VLSI Test Symposium (VTS05), Palm Springs, CA, May 2005.
CN	·	G.  Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Reliability and Performance in the Memory Hierarchy,” Proc. of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS05), Austin, Texas, March 2005.
CN	·	G. Asadi and M. B. Tahoori, “An Accurate SER Estimation Method Based on Propagation Probability,” Proc. of the IEEE Design, Automation and Test in Europe Conference (DATE’05), March 2005.
CN	·	G.. Asadi and M. B. Tahoori, “Soft Error Rate Estimation and Mitigation for SRAM-Based FPGAs,” Proc. of the 13^th ACM International Symposium on Field-Programmable Gate Arrays (FPGA-2005) , Monterey,  CA, Feb. 2005.
CN	·	G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs,” Proc. of the MAPLD04 Conference, Washington DC, September 2004.

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