Publications

2005

2004

2003

2002

2001

JN: Journal Paper

CN: Conference Paper

2005:

CN	·	H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Reliability Tradeoffs in Design of Cache Memories,” Accepted in the Workshop on Architectural Reliability (WAR-1), held in conjunction with 38th International Symposium on Microarchitecture (MICRO-38), Barcelona, Spain, Dec. 2005.
CN	·	H. Asadi and M. B. Tahoori, “Soft Error Modeling and Protection for Sequential Elements”, Proc. of the IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), pp. 463-471, Monterey, CA, Oct. 2005.
CN	·	G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation in Digital Circuits,” Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 2005.
CN	·	G.  Asadi and M. B. Tahoori, “Soft Error Mitigation for SRAM-Based FPGAs,” Proc. of the 23^rd IEEE VLSI Test Symposium (VTS05), Palm Springs, CA, May 2005.
CN	·	G.  Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Reliability and Performance in the Memory Hierarchy,” Proc. of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS05), Austin, Texas, March 2005.
CN	·	G. Asadi and M. B. Tahoori, “An Accurate SER Estimation Method Based on Propagation Probability,” Proc. of the IEEE Design, Automation and Test in Europe Conference (DATE’05), March 2005.
CN	·	G.. Asadi and M. B. Tahoori, “Soft Error Rate Estimation and Mitigation for SRAM-Based FPGAs,” Proc. of the 13^th ACM International Symposium on Field-Programmable Gate Arrays (FPGA-2005) , Monterey,  CA, Feb. 2005.

2004:

CN	·	G. Cardarilli, M. Ottavi, S. Pontarelli , M. Re, A. Salsano, "Data Integrity Evaluations of Reed Solomon Codes for Storage Systems", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, Cannes, France, October 2004.
CN	·	X. Wang, M. Ottavi, F. Lombardi, "Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs.", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004 , Cannes, France, October 2004
CN	·	X. Wang, M. Ottavi, F. Meyer, F. Lombardi, "On The Yield of Compiler-based eSRAMs", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, Cannes, France, October 2004
CN	·	G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs,” Proc. of the MAPLD04 Conference, Washington DC, September 2004.
CN	·	J. Huang, M. B. Tahoori, F. Lombardi, “Routability and Fault Tolerance of FPGA Interconnect Architectures,” In International Test Conference, 2004.
CN	·	J. Huang, M. Momenzadeh, M. B. Tahoori, F. Lombardi, “Defect Characterization for Scaling of QCA Devices,” In IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004.
CN	·	L. Schiano, M. Ottavi, F. Lombardi, "Markov Models of Fault-Tolerant Memory Systems Under SEU", IEEE International Workshop on Memory Technology, Design and Testing , San Jose' CA, August 2004
CN	·	J. Huang, M. B. Tahoori, F. Lombardi, “On the Defect Tolerance of Nano-scale Two-Dimensional Crossbars,” In IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004.
JN	·	M. B. Tahoori, J. Huang, M. Momenzadeh, F. Lombardi, “Testing of Quantum Cellular Automata,” In IEEE Transaction on Nanotechnology, accepted.
JN	·	M. B. Tahoori, S. Mitra, “Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configuration,” In IEEE Transaction on Computer Aided Design of Integrated Circuits, February 2004.
CN	·	J. Huang, M. Momenzadeh, M.B. Tahoori, and F. Lombardi, “Design and Characterization of An And-Or-Inverter (AOI) Gate for QCA Implementation”, In Great Lake Symposium on VLSI (GLSVLSI), 2004.
CN	·	M. Momenzadeh, M.B. Tahoori, J. Huang, and F. Lombardi, “Quantum Cellular Automata: New Defects and Faults for New Devices”, In Fault Tolerance in Parallel and Distributed Systems (FTPDS) Workshop, 2004.
CN	·	M.B. Tahoori, J. Huang, M. Momenzadeh and F. Lombardi, “Defects and Faults in Quantum Cellular Automata at Nano Scale”, In 22^nd VLSI Test Symposium, 2004.
CN	·	J. Huang, M.B. Tahoori, and F. Lombardi, “Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array”, In Reconfigurable Architectures Workshop, 2004.
CN	·	M. B. Tahoori, S. Mitra, “Fault Detection and Diagnosis Techniques for Molecular Computing”, In NanoTech, 2004.
CN	·	M.B. Tahoori, J. Huang, M. Momenzadeh and F. Lombardi, “Defect and Fault Characterization in Quantum Cellular Automata”, In NanoTech, 2004.
CN	·	R. Murgai, M. B. Tahoori, S. Reddy, T. Miyoshi, T. Hiore, “Sensitivity-Based Modeling and Methodologies for Full-Chip Substrate Noise Analysis,” In Design Automation and Test in Europe (DATE) Conference, 2004.
CN	·	M. B. Tahoori, F. Lombardi, “Testing of Quantum Dot Cellular Automata Based Designs”, In Design Automation and Test in Europe (DATE) Conference, 2004.
CN	·	J. Huang, M.B. Tahoori, and F. Lombardi, “Fault Tolerance of Programmable Switch Blocks”, In Design Automation and Test in Europe (DATE) Conference, 2004.

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2002:

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