Information about Dependable Nano-Computing Laboratory (DNL)

Welcome to Dependable Nano-Computing Lab (DNL) at the Electrical & Computer Engineering Department at Northeastern University, Boston, MA.

The DNL laboratory was established in 2003. The overall activity at DNL focuses on test and reliability issues in VLSI and nano systems.

The current research includes:

· Design and test automation, defect and fault tolerance in Crossbar array nano-architectures

· Design, test, and fault tolerance of Quantum-dot Cellular Automata (QCA)

· Soft Error modeling and mitigation in VDSM VLSI

· System-level dependability analysis

· Fault tolerance of FPGA architectures

· Software Reliability

· Automatic Test Pattern Generation (ATPG) for timing failures

· Reliability issues in very deep sub-micron (VDSM) VLSI designs 

· System Biology (Analysis of complex molecular pathways in human disorders)

The current research activities are organized into the following projects:

· Defect and Fault Tolerance for Crossbar Nano-Architectures

· Soft Error Reliability Modeling and Mitigation at Nanoscale

• System Level Soft Error Rate Estimation

• Soft Error Rate Estimation and Mitigation of SRAM-Based FPGAs

• Reliability of the Cache Memory Hierarchy

• System-level Dependability Modeling and Analysis

· Quantum dot Cellular Automata (QCA)

· VLSI Test

· FPGA Test and Fault Tolerance

· Mixed Signal CAD

· System Biology