**GRAPE: A Graph-Based
Power Estimator for CMOS Circuits **

*Introduction*

With the current focus on designing VLSI circuits for low power, there is a growing need for tools that can accurately estimate power dissipation. Estimates of both average and worst-case power are extremely valuable in the design phase.

Power estimation methods implemented thus far tend to be based either on circuit simulation or probability propagation. Both of these varieties of methods have their advantages and disadvantages. In this paper, we propose a hybrid graph-based method that combines the better qualities of both of these categories.

GRAPE uses a novel method that encapsulates the
*behavior *of a circuit into a graph, rather than the circuit structure.
From this behavior graph, worst-case or average power can be estimated
with a series of graph algortihms and approximations with far more accuracy
than traditional methods.

Some of the advantages of this method over opreviously proposed methods are:

- Quickly computes estimates of average power, worst-case power and worst-case sustainable power.
- Computes power dissipated due to glitching without delay modeling.
- Two methods for power computation: probabilistic or simulation-based.
- Easily adaptable for power estimation in the presence of additional knowledge about the circuit's inputs.
- Straightforward extensions for accurate power estimation for sequential circuits.

*Description*

The basic flow of the estimator is as follows:

- read circuit
- convert circuit to structural graph format
- partition structural graph
- convert structural graphs into behavioral graphs
- estimate partition power
- combine partition estimates for full-circuit estimate

As noted above, the behavioral graph is obtained from a structural representation of the circuit. As the behavioral representation (basically a compressed truth table) must be complete, this step requires an exponential algorithm that produces a behavior graph that is expoential in the number of gates in the circuit. Therefore, much of the estimation algortihm is concentrated on reducing the complexity of the circuit while retaining a high level of accuracy.