--======================================================--

--                      LIBRARIES                       --

--======================================================--



-- IEEE Libraries --

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

--use IEEE.std_logic_signed.all;


-- Wildstar System Libraries -
--library SYSTEM;
--use SYSTEM.Xilinx_Package.all;
--use SYSTEM.AMS_package.all;

-- LAD Mux Libraries --
--library LAD_Mux_Lib;
--use LAD_Mux_Lib.LAD_Mux_pkg.all;

-- Mem Mux Libraries --
--library Mem32_Mux_Lib, Mem64_Mux_Lib;
--use Mem32_Mux_Lib.Mem32_Mux_pkg.all;
--use Mem64_Mux_Lib.Mem64_Mux_pkg.all;

-- float

library work;
use work.float_pkg.all;

----------------------------------------------------------
--           IEEE Single Precision Substractor          --
----------------------------------------------------------

entity single_precision_substractor is
	port
	(
		--inputs
		IN1		: in	std_logic_vector(31 downto 0);
		IN2		: in	std_logic_vector(31 downto 0);
		READY		: in	std_logic;
		EXCEPTION_IN	: in	std_logic;
		ROUND		: in	std_logic;
		CLK		: in	std_logic;
		--outputs
		OUT1		: out	std_logic_vector(31 downto 0) := (others=>'0');
		EXCEPTION_OUT	: out	std_logic		      := '0';
		DONE		: out	std_logic		      := '0'
	);
end single_precision_substractor;


----------------------------------------------------------
--           IEEE Single Precision Substractor          --
----------------------------------------------------------

architecture single_precision_substractor_arch of single_precision_substractor is
	signal	rd1 	: std_logic	:= '0';
	signal	rd2	: std_logic	:= '0';
	signal	rd3	: std_logic	:= '0';
	signal	rd4	: std_logic	:= '0';
	signal	exc1	: std_logic	:= '0';
	signal	exc2	: std_logic	:= '0';
	signal	exc3	: std_logic	:= '0';
	signal	exc4	: std_logic	:= '0';
	signal	rnd1	: std_logic	:= '0';
	signal	rnd2	: std_logic	:= '0';
	signal	rnd3	: std_logic	:= '0';
	signal	rnd4	: std_logic	:= '0';
	signal	op1	: std_logic_vector(32 downto 0)	:= (others=>'0');
	signal	op2	: std_logic_vector(32 downto 0)	:= (others=>'0');
	signal	sum	: std_logic_vector(33 downto 0)	:= (others=>'0');

begin

	--instances of components
	denorm1: denorm
		generic map
		(
			exp_bits	=>	8,
			man_bits	=>	23
		)
		port map
		(
			--inputs
			IN1		=>	IN1,
			READY		=>	READY,
			EXCEPTION_IN	=>	EXCEPTION_IN,
			--outputs
			OUT1		=>	op1,
			DONE		=>	rd1,
			EXCEPTION_OUT	=>	exc1
		);


	denorm2: denorm
		generic map
		(
			exp_bits	=>	8,
			man_bits	=>	23
		)
		port map
		(
			--inputs
			IN1		=>	IN2,
			READY		=>	READY,
			EXCEPTION_IN	=>	EXCEPTION_IN,

			--outputs
			OUT1		=>	op2,
			DONE		=>	rd2,
			EXCEPTION_OUT	=>	exc2
		);

	substractor: fp_sub

		generic map
		(
			exp_bits	=>	8,
			man_bits	=>	24
		)
		port map
		(
			--inputs
			OP1		=>	op1,
			OP2		=>	op2,
			READY		=>	rd3,
			EXCEPTION_IN	=>	exc3,
			CLK		=>	CLK,

			--outputs
			RESULT		=>	sum,
			EXCEPTION_OUT	=>	exc4,
			DONE		=>	rd4
		);

	rnd_norm1: rnd_norm

		generic map
		(
			exp_bits	=>	8,
			man_bits_in	=>	25,
			man_bits_out	=>	23
		)

		port map
		(
			--inputs
			IN1		=>	sum,
			READY		=>	rd4,
			CLK		=>	CLK,
			ROUND		=>	rnd4,
			EXCEPTION_IN	=>	exc4,
			--outputs
			OUT1		=>	OUT1,
			DONE		=>	DONE,
			EXCEPTION_OUT	=>	EXCEPTION_OUT
		);

	rd3	<=	rd1 AND rd2;
	exc3	<=	exc1 OR	exc2;


	main: process (CLK)
	begin
		if(rising_edge(CLK)) then
			rnd4	<=	rnd3;
			rnd3	<=	rnd2;
			rnd2	<=	rnd1;
			rnd1	<=	ROUND;
		end if;--CLK

	end process;--main

	
end single_precision_substractor_arch;--end of architecture