library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


entity single_precision_squareroot is
	generic
	(
		exp_bits	:	integer;
		man_bits	:	integer
	);
	port
	(
		--inputs
		OP		:	in		std_logic_vector(exp_bits+man_bits downto 0);
		READY		:	in		std_logic;
		EXCEPTION_IN	:	in		std_logic;
		CLK		:	in		std_logic;
		--outputs
		RESULT		:	out		std_logic_vector(exp_bits+man_bits downto 0);
		EXCEPTION_OUT	:	out		std_logic																					:=	'0';
		DONE		:	out		std_logic																					:=	'0'
	);
end single_precision_squareroot;


architecture single_precision_squareroot_arch of single_precision_squareroot is

component fp_sqrt is
	generic
	(
		exp_bits	:	integer;
		man_bits	:	integer
	);
	port
	(
		--inputs
		OP		:	in		std_logic_vector(exp_bits+man_bits+1 downto 0);
		READY		:	in		std_logic;
		EXCEPTION_IN	:	in		std_logic;
		CLK		:	in		std_logic;
		--outputs
		RESULT		:	out		std_logic_vector(exp_bits+((man_bits+3)/4+1)*4+1 downto 0);
		EXCEPTION_OUT	:	out		std_logic;
		DONE		:	out		std_logic
	);
end component;

component denorm is
	generic
	(
		exp_bits		:	integer;
		man_bits		:	integer
	);
	port
	(
		--inputs
		IN1		:	in		std_logic_vector(exp_bits+man_bits downto 0);
		READY		:	in		std_logic;
		EXCEPTION_IN	:	in		std_logic;
		--outputs
		OUT1		:	out		std_logic_vector(exp_bits+man_bits+1 downto 0);
		DONE		:	out		std_logic;
		EXCEPTION_OUT	:	out		std_logic
	);
end component;

component rnd_norm is
	generic
	(
		exp_bits	:	integer;
		man_bits_in	:	integer;
		man_bits_out	:	integer
	);
	port
	(
		--inputs
		IN1		:	in		std_logic_vector((exp_bits+man_bits_in) downto 0);
		READY		:	in		std_logic;
		CLK		:	in		std_logic;
		ROUND		:	in		std_logic;
		EXCEPTION_IN	:	in		std_logic;
		--outputs
		OUT1		:	out		std_logic_vector((exp_bits+man_bits_out) downto 0);
		DONE		:	out		std_logic;
		EXCEPTION_OUT	:	out		std_logic
	);
end component;

--======================================================--
--                      SIGNALS                         --
--======================================================--
constant    sq_bits	:integer	:= (man_bits+3)/4+1;
constant    f_bits	: integer	:= sq_bits * 4;
	
signal	opl : std_logic_vector(exp_bits+man_bits+1 downto 0);
signal	sq_out : std_logic_vector(exp_bits+f_bits+1 downto 0);
signal	rdy1, rdy2, exc1, exc2 : std_logic;
	
begin
----------------------------------------------------------
--               Component Instantiation                --
----------------------------------------------------------

denorm1: denorm
	generic map
	(
		exp_bits	=>	exp_bits,
		man_bits	=>	man_bits
	)
	port map
	(
		--inputs
		IN1		=>	op,
		READY		=>	READY,
		EXCEPTION_IN	=>	EXCEPTION_IN,
		--outputs
		OUT1		=>	opl,
		DONE		=>	rdy1,
		EXCEPTION_OUT	=>	exc1
	);

fpsq: fp_sqrt 
	generic map
	(
		exp_bits	=>	exp_bits,
		man_bits	=>	man_bits
	)
	port map
	(
		--inputs
		OP		=>	opl,
		READY		=>	rdy1,
		EXCEPTION_IN	=>	exc1,
		CLK		=>	clk,
		--outputs
		RESULT 		=>	sq_out,
		EXCEPTION_OUT 	=>	exc2,
		DONE 		=>	rdy2
	);

rndnorm: rnd_norm 
	generic map
	(
 		exp_bits	=>	exp_bits,
		man_bits_in	=>	f_bits+1,
		man_bits_out	=>	man_bits
	)
	port map
	(
		--inputs
		IN1		=>	sq_out,			
		READY		=>	rdy2,			
		CLK		=>	clk,
		ROUND		=>	'0',
		EXCEPTION_IN	=>	exc2,
		--outputs
		OUT1		=>	result,	
		DONE		=>	done,
		EXCEPTION_OUT 	=>	exception_out
	);

end single_precision_squareroot_arch;