library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


entity single_precision_divider is
	generic
	(
		exp_bits	:	integer;
		man_bits	:	integer
	);
	port
	(
		--inputs
		OP1		:	in	std_logic_vector(exp_bits+man_bits downto 0);
		OP2		:	in	std_logic_vector(exp_bits+man_bits downto 0);
		READY		:	in	std_logic;
		EXCEPTION_IN	:	in	std_logic;
		CLK		:	in	std_logic;
		--outputs
		RESULT		:	out	std_logic_vector(exp_bits+man_bits downto 0);
		EXCEPTION_OUT	:	out	std_logic																					:=	'0';
		DONE		:	out	std_logic																					:=	'0'
	);
end single_precision_divider;


architecture single_precision_divider_arch of single_precision_divider is

component fp_div is
	generic
	(
		exp_bits	:	integer;
		man_bits	:	integer
	);
	port
	(
		op1		:	in	std_logic_vector(exp_bits+man_bits+1 downto 0);
		op2		:	in	std_logic_vector(exp_bits+man_bits+1 downto 0);
		READY		:	in	std_logic;
		EXCEPTION_IN	:	in	std_logic;
		CLK		:	in	std_logic;
		RESULT		:	out	std_logic_vector(exp_bits+man_bits+2 downto 0);
		EXCEPTION_OUT	:	out	std_logic																					:=	'0';
		DONE		:	out	std_logic																					:=	'0'
	);
end component;

component denorm is
	generic
	(
		exp_bits		:	integer;
		man_bits		:	integer
	);
	port
	(
		--inputs
		IN1		:	in		std_logic_vector(exp_bits+man_bits downto 0);
		READY		:	in		std_logic;
		EXCEPTION_IN	:	in		std_logic;
		--outputs
		OUT1		:	out		std_logic_vector(exp_bits+man_bits+1 downto 0);
		DONE		:	out		std_logic;
		EXCEPTION_OUT	:	out		std_logic
	);
end component;

component rnd_norm is
	generic
	(
		exp_bits	:	integer;
		man_bits_in	:	integer;
		man_bits_out	:	integer
	);
	port
	(
		--inputs
		IN1		:	in		std_logic_vector((exp_bits+man_bits_in) downto 0);
		READY		:	in		std_logic;
		CLK		:	in		std_logic;
		ROUND		:	in		std_logic;
		EXCEPTION_IN	:	in		std_logic;
		--outputs
		OUT1		:	out		std_logic_vector((exp_bits+man_bits_out) downto 0);
		DONE		:	out		std_logic;
		EXCEPTION_OUT	:	out		std_logic
	);
end component;

--======================================================--
--                      SIGNALS                         --
--======================================================--
signal	op1l : std_logic_vector(exp_bits+man_bits+1 downto 0);
signal	op2l : std_logic_vector(exp_bits+man_bits+1 downto 0);

signal	rdy1, rdy2, rdy3, rdy4 : std_logic;
signal  exc1, exc2, exc3, exc4 : std_logic;

signal	div_out : std_logic_vector(exp_bits+man_bits+2 downto 0);

	
begin

rdy3 <= rdy1 and rdy2;
exc3 <= exc1 or exc2;

----------------------------------------------------------
--               Component Instantiation                --
----------------------------------------------------------
denorm1: denorm
	generic map
	(
		exp_bits	=>	exp_bits,
		man_bits	=>	man_bits
	)
	port map
	(
		--inputs
		IN1		=>	op1,
		READY		=>	READY,
		EXCEPTION_IN	=>	EXCEPTION_IN,
		--outputs
		OUT1		=>	op1l,
		DONE		=>	rdy1,
		EXCEPTION_OUT	=>	exc1
	);

denorm2: denorm
	generic map
	(
		exp_bits	=>	exp_bits,
		man_bits	=>	man_bits
	)
	port map
	(
		--inputs
		IN1		=>	op2,
		READY		=>	READY,
		EXCEPTION_IN	=>	EXCEPTION_IN,
		--outputs
		OUT1		=>	op2l,
		DONE		=>	rdy2,
		EXCEPTION_OUT	=>	exc2
	);    

fpdiv: fp_div
	generic map
	(
		exp_bits	=>	exp_bits,
		man_bits	=>  man_bits
	)
	port map
	(
		--inputs
		OP1		=>	op1l,
		OP2		=>	op2l,
	    	READY		=>	rdy3,
		EXCEPTION_IN	=>	exc3,
		CLK		=>	clk,
		--outputs
		RESULT		=>	div_out,
		EXCEPTION_OUT	=>	exc4,
		DONE		=>	rdy4
	);

rndnorm: rnd_norm 
	generic map
	(
 		exp_bits	=>	exp_bits,
		man_bits_in	=>	man_bits+2,
		man_bits_out	=>	man_bits
	)
	port map
	(
		--inputs
		IN1		=>	div_out,			
		READY		=>	rdy4,			
		CLK		=>	clk,
		ROUND		=>	'0',
		EXCEPTION_IN	=>	exc4,
		--outputs
		OUT1		=>	result,	
		DONE		=>	done,
		EXCEPTION_OUT 	=>	exception_out
	);

end single_precision_divider_arch;