Systems with FPGAs in them are inherently hardware/software systems. The
simplest of these systems have one host processor and one FPGA both of
which are used for computation. We are developing tools to determine when
to best make use of the FPGA hardware. Our tools are unique in that they
take into account communication costs and overhead costs and not just the
raw computational speedup from running an algorithm on FPGA hardware. Our
tool focuses on image processing pipelines. It determines what to run in
hardware and what in software, generates the pipeline implementation, and
runs it. We will extend this work to other application domains as well as
to more sophisticated systems with several FPGAs and several processors.
New FPGA devices have embedded processors on the chip with the
reconfigurable logic. We are investigating how best to make use of these
embedded processors and how best to interface them to the FPGA logic. In
addition, we are investigating ways to quantify computation times for
algorithms run on the different types of resources available, including
the overhead costs incurred in the interfaces. The goal is to predict how
best to partition an application between hardware and software. For this
research, we are using software defined radio as a target application.
Variable Precision Arithmetic
Many of the applications used for FPGAs are scientific applications that
require floating point representations of numbers. The goal of using
FPGAs is to exploit low-level parallelism and to do as many computations
in parallel as possible. In order to support both floating point
representations and a high degree of parallelism, we have developed a
library of FPGA components that implement basic floating point arithmetic
functions including add, subtract, multiply, divide and square root.
The hardware modules are fully parameterized.
These components support the IEEE standard floating point formats, and
also formats with reduced bit-widths to enable higher degrees of
VSIPL++ is the C++ version of the Vector/Signal/Image Processing Library, a
library of C and C++ routines for simply and efficiently writing programs to
perform standard signal processing functions. This project seeks to create a
framework to ease the inclusion of hardware algorithm accelerators
(specifically those targeted for FPGAs) in VSIPL++ code development.
Backprojection is the most common algorithm used in the tomographic
reconstruction of a clinical data. An everyday example of tomographic is the
medical x-ray CAT scan: a person is x-rayed from various angles and the
two-dimensional density of the person can be "reconstructed" by using
backprojection. However, the restoration is computation consuming. The project
goal is to implement backprojection algorithm in reconfiguable hardware thus
greatly decrease the processing time.
The Finite-Difference Time-Domain (FDTD) method is one of the most
popular numerical methods for the solution of problems in
electromagnetics. It is used for analyzing radar cross sections of
airplanes, siting cell phone towers, and finding breast tumors, among
The 3D FDTD algorithm can be used on buried object detection areas.
One of the challenges to using FDTD is the large
amount of computation required. We have a project to accelerate FDTD
using FPGAs. Target applications are finding buried land mines and
finding skin cancers in situ using confocal microscopy.
PIV is an important technique used in
Fluid Dynamics to determine the flow of particles in a fluid. PIV is a
whole-flow-field technique providing instantaneous velocity vector
measurements in a cross-section of a flow. PIV computes instantaneous 3D
velocity vectors for an area of interest. Applications of PIV include
combustion research, aircraft design studies, unsteady aerodynamic and
turbulent water channel flows, and weather simulation. We are using FPGAs
to accelerate PIV so that real-time PIV information can be used for
control, for example for controlling the flaps of airfoils using real-time
Phase unwrapping is the process of recovering phase information that
has been constrained to cycle through the range between -pi and pi.
Getting the original phase information is necessary for interference
based imaging such as that used in the Optical Quadrature
Microscope(OQM). Robust methods for performing this task are very
computationally intensive in nature. The goal of this project is to
identify the key components of such algorithms and implement them in
Reconfigurable Hardware is used to accelerate an existing real-time
algorithm for tracing of the vasculature and an alysis of intersections
and crossovers in live high-resolution retinal fundus image sequences.
Past Research Projects
A high level hardware description language and its translation toVHDL.
Environmental monitoring, earth resource mapping, and military systems
require broad-area imaging at high resolutions. Many times the imagery
must be acquired in inclement weather or during night as well as day.
Synthetic Aperture Radar (SAR) provides such a capability. SAR systems
take advantage of the long-range propagation characteristics of radar
signals and the complex information processing capability of modern
digital electronics to provide high resolution imagery. Synthetic
aperture radar complements photographic and other optical imaging
capabilities because of the minimum constraints on time-of-day and
atmospheric conditions and because of the unique responses of terrain and
other targets to radar frequencies. We are developing an FPGA system for
reconstructing images from SAR data. This project makes use of a Beowulf
cluster owned by the DOD which has 48 nodes with an FPGA board at every
node. One of the goals of this project is to investigate both the fine
grained and coarse grained parallelism available on this cluster, and see
how it can best be used to accelerate SAR processing.