Once upon a time, when the RPL web pages were current, I was a graduate student at Cornell University working as a visiting scientist at Northeastern University.
That's changed. I completed my Ph.D. in the spring of 1999. In the fall of 1999 I moved back to the San Francisco Bay Area (for those paying attention, I moved from California to Boston to New York then back to Boston and then back to California) to seek my fortune in the EDA industry. I'm currently working for Simplex Solutions, Inc. and live in Downtown San Jose, CA.
My thesis research was in vectorless (aka probabalistic) power estimation of VLSI design. My dissertation included a prototype of a power estimator using a graph-based approach, GRAPE. Might I warn that the material to be found via that link is very out of date. (GRAPE is so obsolete that there's no point worrying about it.)
"A Graph-Based Power Estimation Method for Combinational CMOS Circuits", Technical Report ECE-CEG-98-023, Northeastern University, July 1998. (with Miriam Leeser).
"Accurate Power Estimation for Sequential CMOS Circuits Using Graph-based Methods," in VLSI Design, Vol. 12, No. 2, pp. 187-203, 2001. (with Miriam Leeser).