Our research focuses on mapping image and signal processing applications to reconfigurable hardware. There are two pieces to this research: mapping algorithms to hardware architectures and developing new tools for automatically generating hardware. Our aim is to provide tools and techniques that allow designers to focus on design tradeoffs, and to improve methods for automatically generating designs. In the lab we use a combination of research and commercial tools, as well as the hardware needed to map designs onto field programmable logic.

Professor Miriam Leeser (mel at ece.neu.edu) Lab Members Research Projects Publications Donations and Support We would like to thank the following organizations for their donations and support: Synplicity, Xilinx, Intel Corporation, Modelsim, Mercury Computer Systems, CENSSIS and NSF.

Field Programmable Gate Instructions for building one :)

This page is maintained by M. Leeser (mel at ece.neu.edu) URL: http://www.ece.neu.edu/groups/rpl/index.html