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Development of a DSP Compilation Testbed
Research Students:
Suleyman Sair
Songqing Zhang 		Faculty:
David Kaeli
Waleed Meleis
John Proakis

Project Summary:
D igital Signal Processors (DSPs) are used to implement a wide range of performance-critical telecommunications and signal processing applications. The impact of these applications is growing, allowing DSPs to continue to be an important architectural platform.

Currently, the majority of all DSP programs are written in assembly code. This fact is disturbing, given the amount of effort expended developing optimizing compiler technology for general purpose microprocessors (e.g., PowerPC, Pentium, and UltraSPARC). One reason for this reluctance is that since high-end DSP processors possess some highly irregular architectural features (e.g., non-orthogonal instruction sets, VLIW-like instruction issue units), such that many of the compiler optimizations typically applied to code targeted for general purpose microprocessors are not applicable to DSP applications. Thus, programmers in search of high performance still need to fall back on hand coding in assembly.

The pitfalls of coding in assembly are many, but are dominated by the cost of code maintenance. Writing applications in assembly contradicts many of the underlying principles of Software Engineering. Assembly lanuage code is costly to develop, error prone, and a nightmare to maintain. Improvements in compilation technology targeting DSP will encourage programmers to write their DSP applications in high-level (possibly object-oriented) languages. If DSP code development remains dominated by assembly code, this may force DSP processors into obsolence in favor of more cost-effective (though potentially lower performing) traditional microprocessors.

This project looks to develop a DSP testbed to explore profile-driven compiler optimizations. The goal is to effectively exploit the current wealth of compiler technology present for traditional microprocessors, applying this technology to DSP architectures. We also will propose new compilation algorithms based on improved memory coloring and instruction scheduling techniques.

In Dec. 1997, the National Science Foundation provided a grant (NCRI-97-29856) to purchase DSP software and hardware to support this research.

Publications:
  1. " A Study of Loop Unrolling for VLIW-based DSP Processors " Suleyman Sair, David R. Kaeli, and Waleed Meleis
    1998 IEEE Workshop on SIGNAL PROCESSING SYSTEMS (SiPS '98) , Boston, MA 1998.

  2. " A Study of Dynamic Branch Predication for SHARC DSP's " Suleyman Sair, David Kaeli and Jose Fridman,
    Proc. of the 2nd International Workshop on Compiler and Architecture Support for Embedded Systems (CASES99),
    Washington, D.C., Oct.1999.

  3. " DSPTune - A Performance Toolkit for the SHARC DSP " Suleyman Sair, David Kaeli and Jose Fridman,
    Proc. of SHARC'99 , Herefordshire, England, November 1999.


  4. " DSPTune: A Performance Evaluation Toolset for the SHARC Signal Processor " Suleyman Sair, Guiseppe Olivadoti, David Kaeli and Jose Fridman, in the Proceedings of the 33rd Simulation Symposium , April, 2000, pp. 51-57.

  5. " BDSPTune: A Binary Instrumentation Toolset for the SHARC DSP"
    		Songqing Zhang and David Kaeli,
    Proc. of SHARC'00 , Boston, MA, September 200.



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