Boston Area Computer Architecture Research Workshop
FINAL PROGRAM
8:30-8:40 Welcome: David Kaeli and Csaba Andras Moritz
8:40-9:15 Session chair: Joel Emer, Intel Labs
Keynote: “Where Do We Go from Here? My Thoughts on Computer Architecture,” Jack Dennis, MIT, Fellow of ACM and IEEE
9:15-10:15 Session 1: Power Management
Session Chair: Krste Asanovic, MIT
§
Reducing Power with a Dynamically
Reconfigurable Issue Queue, Yu Bai and Iris Bahar, Brown University
§
Energy-Aware Memory Access Scheduling, Yongkui Han
and Israel Koren, Univ. of Massachusetts, Amherst
§
Power Reduction with
Transactional Memory, Tali Moreshet, Maurice Herlihy R. Iris Bahar and
Richard Weiss, Brown
University and Hampshire College
10:15-10:40 Break
10:40-12:00 Session 2: Memory Systems
Session chair: Dominique Thiebaut,
Smith College
§ Address Correlation: Exceeding the Limits of Locality, Resit Sendag, Univ. of Rhode Island, Peng-fei Chuang and David Lilja, Univ. of Minnesota
§ Fast Query Processing using Cooperative Caching for Index Structures, Gene Cooperman and Xiaoqin Ma, Northeastern Univ.
§ Processor Memory Networks Based on Steiner Systems, Tom Van Court and Martin Herbordt, Boston University
§ Boundless Hardware Transactional Memory, Scott Ananian, Krste Asanovic, Bradley Kuszmaul, Charles Leiserson and Sean Lie, MIT
12:00-1:00 Lunch
1:00-1:30 Session chair: Israel Koren, Univ. of Massachusetts, Amherst
Afternoon Keynote: “Soft Errors in Microprocessors,” Shubu Mukherjee, Intel Labs
1:30-2:30 Session 3: Emerging Technologies
Session chair: R. Iris Bahar, Brown Univ.
§ Exploring Nanoscale Application-Specific ICs and Architectures, Teng Wang and Csaba Andras Moritz, Univ. of Massachusetts, Amherst
§ Exploring Parallel Out-of-order Re-execution, David Morano and David Kaeli, Northeastern Univ.
§ Evaluating the Raw Microprocessor, Michael Taylor and Anant Agarwal, MIT
2:30-2:55 Break
2:55-4:15 Session 4: Registers, Memory Systems and I/O
Session chair: Eliot Moss, University of Massachusetts, Amherst
§
Banked
Register Files for SMT Processors, Jessica Tseng and Krste Asanovic MIT
§
A Unified Cache Coherence and Synchronization Protocol,
Zhenghua Qi, Raksit Ashok, Richard Weiss and Csaba Andras Moritz, Univ. of
Massachusetts, Amherst and Hampshire College
§
Cost-Effective Remote Mirroring Using the iSCSI
Protocol, Ming Zhang and Yinan Liu, Univ. of Rhode Island
§
Energy Characterization of Hardware Data Prefetching,
Yao Guo, Saurabh Chheda, Israel Koren, Mani Krishna, and Csaba Andras Moritz,
Univ. of Massachusetts, Amherst
4:15-4:30 Break
4:30-5:30 Session 5: Security and Simulation
Session chair: Gene Cooperman, Northeastern Univ.
§ Microarchitectural Features to Guard Against Stack Smashing, Dong Ye, Micha Moffie and David Kaeli, Northeastern University
§
CMDL: Class Based Machine Description Language for
Co-generation of Compilers and Simulators, Eliot Moss, Trek Palmer, Timothy
Richards, Edward Walters and Charles Weems, Univ. of Massachusetts, Amherst
§
Workload Analysis for Network Processor Design,
Ramaswamy Ramaswamy, Nick Weng and Tilman Wolf, Univ. of Massachusetts, Amherst
5:30 Workshop
Concludes