Publication
Paper (Journal)
- Byunghyun Jang, Yong-Bin Kim, F. Lombardi``Monomo Control For Error Tolerance In DNA Self-Assembly'',", Journal of Electronic Testing: Theory and Application, Vol. 24, Numbers 1-3, June, 2008, pp.271-284.
- Kyung Ki Kim and Yong-Bin Kim, `` Kyung Ki Kim, Jing Huang, Yong-Bin Kim, and Fabrizio Lombardi ``Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels", IEEE Transactions on Industrial Informatics, Vol. 4, No. 2, May 2008, pp. 134-143.Kyung Ki Kim and Yong-Bin Kim, `` Kyung Ki Kim and Yong-Bin Kim, ``Design Methodology for Power Supply Noise and Leakage Current Control in Nanoscale CMOS VLSI Systems Design", IEEE Transactions on VLSI Systems(accepted).Kyung Ki Kim and Yong-Bin Kim, ``Input Pattern Generation for Leakage Power Reduction Based on Optimal Supply Voltage and Body Voltage'', IEICE Electronics Express(ELEX)(Submitted)Kyung Ki Kim and Yong-Bin Kim, ``Phase Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology '', Journal of Semiconductor Technology and Science, Vol. 7, Number 4, December 2007, pp. 161-166.Kyung Ki Kim and Yong-Bin Kim, ``Statistical Timing and Leakage Power Analysis of PD-SOI Digital Circuits'', '', Analog Integrated Circuits and Signal Processing(Submitted)Kyung Ki Kim and Yong-Bin Kim, ``A 32nm and 0.9V CMOS Phased Locked loop with Leakage Current and Power Supply noise Compensation'', Journal of Semiconductor Technology and Science, Vol. 7, Number 1, March 2007, pp. 11-19..Young Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin Kim, ``A Low Power CMOS Electronic Central Pattern Generator Design for Biomimetic Underwater Robot'', Elsevier Neurocomputing Journal, Vol 71, Issue 1-3, December 2007, pp. 284-296..Kyung Ki Kim, Yong-Bin Kim,``Ultra Low Voltage high Speed Schmitt Trigger Circuit in SOI MOSFET Technology'', IEICE Electronics Express(ELEX), Vol. 4 (2007) , No. 19 pp.606-611.Kyung Ki Kim, Yong-Bin Kim, Mimsu Choi, Nohpill Park,``"Leakage Minimization Technique For Nanoscale CMOS VLSI Based On Macro-Cell Modeling'', IEEE Design and Test of Computers, July-August, 2007, pp322-330.Kyung Ki Kim, Yong-Bin Kim, F. Lombardi``Power Supply Network Aware Timing Analysis Using S-Parameter in Nanometer Digital Circuits,", IEEE Design and Test of Computers(submitted)Rui Tang, Fengming Zhang, Yong-Bin Kim, ``Design Metal-Dot Based QCA Circuits Using SPICE Model", Elsevier Microelectronics Journal, Vol. 37/8, Jun. 2006, pp 821-827.Kyung Ki Kim, Y. Kim, Fabrizio Lombardi, N. Park, ``A Novel Statistical Timing and Leakage Power Characterization of Partially-Depleted Silicon-On-Insulator(SOI) Gates''', IEEE Transactions on Instrumentation and Measurement(Under Revision)Dae Woon Kang, Y. Kim, James Doyle, ``A High Performance Fully Digital Synchronous Buck Converter Power Delivery System Based on Finite State Machine'', IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 14, No 3, pp.229-240, March 2006.Young Bok KimY. Kim, J. Doyle, ``A CMOS Low Power Digital Polar Modulator Design for WCDMA Transmitter'', IEEE Transactions on Circuits and Systems(Under Review)Jihyun Lee and Y.Kim, ``ASLIC: A Low Power CMOS Analog Circuit Design Automation``, Elsevier Integration, the VLSI Journal, vol. 39, No. 3, June 2006, pp. 157--181.Fengming Zhang and Y. Kim, ``SET-Based Nano-Circuit Simulation and Design Method Using HSPICE'', Elsevier Microelectronics Journal, Vol 36/8 pp. 741-748.Marco Ottavi, L. Schiano, X. Wang, Y. Kim, F. Lombardi, ``Evaluating the Yield of Repairable SRAM for ATE'', IEEE Transactions on Instrumentation and Measurement, Vol. 55, No. 5, October 2006, pp.1704-1712.Shivakumar Sompur and Y.Kim "An Investigation into Adiabatic Circuits for Deep Sub-Micron VLSI Application", Elsevier Integration, The VLSI Journal(In Press, will appear soon)L. Schiano, Young Jun Lee, T. Kane, Y-B Kim, ``Measuring the Timing Jitter of ATE in the Frequency Domain'', IEEE Transactions on Instrumentation and Measurement, Vol. 55, No. 1, pp280-289, 2006Marco Ottavi, L. Schiano, X. Wang, Y. Kim, F. Lombardi, ``Yield Estimation Method of SRAM Array'', IEEE Transactions on Instrumentation and Measurement, Oct., 2006N. Park, K.M,George, M. Choi, Y. Kim, ``Environmental-based Characterization of SoC-based Instrumentation Systems for Stratified Testing'', IEEE Transactions on Instrumentation and Measurement, vol.54, No.3, Jun. 2005, pp1241-1248.Fengming Zhang and Y. Kim, ``SET-Based Nano-Circuit Simulation and Design Method Using HSPICE'',Elsevier Microelectronics Journal, Vol 36/8, MAr. 2005, pp. 741-748.James T. Doyle, Young Jun Lee, Y.Kim, ``A CMOS Subbandgap Reference Voltage Circuit with 1V Supply Voltage'', IEEE Transactions on Solid State Circuits, January, 2004. pp.252-255M. Choi, N. Park, V. Piuri, Y. Kim, ``Balancing the Redundancy in Embedded Memory Cores for Dependable Systems'', Elsevier Journal of System Architecture-DFT, Special Issue: Design and Test of System on a Chip, Vol. 50, No. 5, pp.281-285, April 2004James T. Doyle, Young Jun Lee, Y.Kim, ``Improved DAC Modeling Techniques Based on Wavelet Theory'', Elsevier Microelectronics Journal, Vol. 35, Issue5, May 2004, pp.451-460Woo Jin Kim and Y. Kim, ``Automating the Design Approach to Wave Pipelined Circuits'' IEEE Design and Test of Computers'', Nov/Dec 2003, pp.51-58.Soha Hassoun, Y. Kim, and F. Lombardi, ``Introduction: Clockless Digital VLSI Circuit'' IEEE Design and Test of Computers'', Nov/Dec 2003, pp.5-8.B. Jin, K.M. George, N. Park, M. Choi, Y.B. Kim, ``Modeling and Analysis of Soft-Test/Repair for CCD-based Digital X-Ray Systems'', IEEE Transactions on Instrumentation and Measurement, Vol.52, No.6, Dec. 2003, pp.1713-1721Young Jun Lee, Fabrizio Lombardi, Y.Kim ``Analysis and Measurement of Timing Jitter Induced by Radiated EMI Noise in Automatic Test Equipment'', IEEE Transactions on Instrumentation and Measurement, Volume 52, Number6 December 2003, pp.1749-1755Shivakumar Sompur and Y.Kim "An Investigation into Adiabatic Circuits for Deep Sub-Micron VLSI Application", Elsevier The VLSI JournalY.Kim, T. Chen, "Assessing Merged DRAM/Logic Merged Technology", Elsevier Integration, the VLSI Journal, pp.179-194, September 1999
Paper (Conference)
Shikha, Yong-Bin Kim, and Minsu Choi "Probabilistic Analysis of Design Mapping in Asynchronous Nanowire Crossbar Systems", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 1-3. 2008, Cambridge, Massachussets(Submitted).
Sheng Lin, Yong-Bin Kim, and F. Lombardi "A Highly-Stable Nanometer Memory for Low Power Design", IEEE International Workshop on Design and Test of Nano Device, Circuits, and Systems(NDCS'08), September 20-30. 2008, Boston, Massachussets(Submitted).
Young Bok Kim, Yong-Bin Kim, and F. Lombardi "Low Power SRAM Design for 32nm Independent Gate FinFE", IEEE International Workshop on Design and Test of Nano Device, Circuits, and Systems(NDCS'08), September 20-30. 2008, Boston, Massachussets(Submitted).
Sheng Lin, Yong-Bin Kim, and F. Lombardi "1 Low Leakage 9T SRAM cell for Ultra-Low Power Operation", ACM GLSVLSI'08(Great Lake Symposium on VLSI), May 4-6, 2008, Orlando, Florida, pp.123-126.
Young Bok Kim, Yong-Bin Kim, and F. Lombardi "A Technique for Low Power Dynamic Circuit Design in 32nm Double Gate FinFET Technology", IEEE International MWSCAS 2008, August 10-13, 2008, Knoxville, Tenesse(Submitted)
Sheng Lin, Yong-Bin Kim, and F. Lombardi"A 32nm SRAM Design for Low Power and High Stability", IEEE International MWSCAS 2008, August 10-13, 2008, Knoxville, Tenesse(Submitted)
Jun Zhao and Yong-Bin Kim, "A 12-bit Digitally Controlled Oscillator with Low Power Consumption and Low Jitter", IEEE International MWSCAS 2008, August 10-13, 2008, Knoxville, Tenesse(Submitted)
Sheng Lin, Yong-Bin Kim, and F. Lombardi, "A Highly Stable Low-Power CMOS Nano-SRAM Design Using Bitline Balancing", IEEE International SOC Conference, Sep. 17-20, 2008, Newport Beach, California(Submitted)
Young Bok Kim, Yong-Bin Kim, and F. Lombardi, "Low Power 8T SRAM Using 32nm Independent Gate FinFET Technology ", IEEE International SOC Conference, Sep. 17-20, 2008, Newport Beach, California(Submitted)
Jun Zhao and Yong-Bin Kim, "A Low Power 32 Nano Meter CMOS Digitally Controlled Oscillator ", IEEE International SOC Conference, Sep. 17-20, 2008, Newport Beach, California(Submitted)
Youong Bok Kim and Yong-Bin Kim, "Fault Tolerant Source Routing for Network-on-chip", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2007, September 26-28, 2007, Rome, Italy, pp.12-20.
Ravi Bonam, Yong-Bin Kim, and Minsu Choi,, "Defect Tolerant Gate Macro Mapping and Placement in Clock-Free Nanowire Crossbar Architecture'", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2007, September 26-28, 2007, Rome, Italy, pp.161-169.
Kyung Ki Kim and Yong-Bin Kim, "Phase-Locked Loop Considering Leakage and Power/Ground Noise", IEEE International SoC Design Conference(ISOCC), October 15-16, 2007, Seoul, Korea, pp.295-298.
Ping Liu and Yong-Bin Kim, "An Accurate Analytical Propagation Delay Model of Nano CMOS Circuits", IEEE International SoC Design Conference(ISOCC), October 15-16, 2007, Seoul, Korea, pp.200-203.
Ping Liu and Yong-Bin Kim, "An Accurate Timing Model for Nano CMOS Circuit Considering Statistical Process Variation", IEEE International SoC Design Conference(ISOCC), October 15-16, 2007, Seoul, Korea, pp.269-272.
Joseph Ayers, Nikolai Rulkov, Dan Knudsen, Yong-Bin Kim, Alexander Volkovskii, Allen Selverston, "Controlling Underwater Robots with Electronic Nervous Systems", IEEE International Conference on Robotics and Automation(ICRA) 2007, April 10-14, 2007, Rome, Italy,TF-1, pp. 1-6
Yong-Bin Kim and James Doyle, " A CMOS CORDIC Processor Design for Wireless Telecommunication ", IEEE Midwest Symposium on Circuit and Systems(with NEWCAS), August 5-8, 2007, Montreal, Canada, pp.1336-1339.
Jun Zhao and Yong-Bin Kim, " Circuit Implementation of FitzHugh-Nagumo Neuron Model Using Field Programmable Analog Array'' ",IEEE Midwest Symposium on Circuit and Systems(with NEWCAS), August 5-8, 2007, Montreal, Canada, pp.772-775.
Kyung Ki Kim, Yong-Bin Kim, ""Probabilistic Leakage Power Estimation of Partially-Depleted Silicon-On-Insulator(SOI) Gates," IEEE Midwest Symposium on Circuit and Systems(with NEWCAS), August 5-8, 2007, Montreal, Canada, pp.980-983.
Rui tang, Yong-Bin Kim, ""Energy Efficient CMOS PWAM Transmitter Design," IEEE Midwest Symposium on Circuit and Systems(with NEWCAS), August 5-8, 2007, Montreal, Canada, pp.1161-1164.
Yong-Bin Kim and James Doyle, " A Low Power Digital Self-Adjusting Adaptive Voltage Scaling System Considering PVT and Loading Variations ", IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007.
Yong-Bin Kim and Kyung Ki Kim, " Optimal Body Biasing for Minimum Leakage Power in Standby Mode ", IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007, pp.1161-1164.
Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi,'' Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer'', Design Automation and Test in Europe, April 16-20,2007 Acropolis Nice, France, pp. 847-852
Byunghyun Jang, Yong-Bin Kim, '' Modeling and Evaluation of Multi-Bank SRAM Design for Leakage Power Reduction'', 2007 Boston Area Architecture(BARC) Workshop, January 26 2007, Booston, MA, pp15-26.
Youngbok Kim, Yong-Bin Kim, '' An Asynchronous NoC Router Architecture Supporting Quality-of-Service'', 2007 Boston Area Architecture(BARC) Workshop, Januray 26 2007, Booston, MA, pp17-18.
Kyung Ki Kim, Jing Huang, Rui Tang, Yong-Bin Kim, and Fabrizio Lombardi, Minsu-Choi "" Analysis and Simulation of Jitter for High Speed Links in Systems-On-Chip Systems ", IMTC 2007 IEEE Instrumentation and Measurement Technology Conference, May 1-3, 2007, Warsaw, Poland, pp.1-4.
Kyung Ki Kim, Jing Huang, Rui Tang, Yong-Bin Kim, and Fabrizio Lombardi, "" Accurate Macro-Modeling for Leakage Current for I(DDQ) Test ", IMTC 2007 IEEE Instrumentation and Measurement Technology Conference, May 1-3, 2007, Warsaw, Poland, pp.1-4.
Josepth Ayers, Nikolai Rulkov, Edward Taub, Yong-Bin Kim, Allen Selverston, Gittendra Uswatte ``Electronic Neurons From Biomimetic Robots to Blast Neuroehabilitation", Seventh International Symposium on Technology and Mine Problem, May. 2-5, 2006, Monterey, CA, Chapter B-3.
Yong-Bin Kim` ` Quantum-Dot Cellular Automata SPICE Macro Model", Global Convention of Ethnic Korean Scientists and Engineers 2006'', Seoul, Korea, July 17-22, 2006, pp171.
Rui Tang, Yong-Bin Kim, ""A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits, ", IEEE SOCC'06(IEEE International SOC Conference), September 24-27, 2006, Austin, Texas, pp.119-122.
Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, "" A Load board Design Using Compound Dot Technique and Phase Detector for Hierarchy ATE Calibrations, "IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Washinton DC, October 4-6, 2006, pp486-494.
Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim, "" Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects, "IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Washinton DC, October 4-6, 2006, pp98-106.
Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi "" Error Tolerance of DNA Self-Assembly by Monomer Concentration Control ", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Washinton DC, October 4-6, 2006, pp89-97.
Rui Tang and Yong-Bin Kim, "" PWAM Signaling Scheme for High Speed Serial Link Tranceiver Design ", ACM GLSVLSI'06(Great Lake Symposium on VLSI), Philadelphia, PA, April 30-May 2 2006, pp.49-52
Kyung Ki Kim and Yong-Bin Kim, "" Ultra Low Voltage VCO Design Using Schmitt Trigger on SOI(Silicon On Insulator) ", IEEE ISOCC'06(IEEE International SOC Conference), October 26-27, 2006, Seoul South Korea, pp127-130.
Rui Tang, Yong-Bin Kim, Minsu Choi and Fabrizio Lombardi, ""Jitter Analysis in High Speed Serial Link Using a PWM Scheme ", IEEE IMTC(Instrumentation and Measurement Technology Conference) 2006, October 2006, Sorrento, Italy, pp.494-497
Kyung Ki Kim, Yong-Bin Kim, N. park, and F. Lombardi, "" Clock Grid Simulation Using Transient S-parameter Modeling", IEEE IMTC(Instrumentation and Measurement Technology Conference) 2006, October 2006, Sorrento, Italy, pp.225-228
Kyung Ki Kim, Yong-Bin Kim, N. park, and F. Lombardi, ""Statistical Characterization of Partially-Depleted SOI Gates'", IEEE IMTC(Instrumentation and Measurement Technology Conference) 2006, October 2006, Sorrento, Italy, pp.245-248
Joseph Ayers, Nikolai Rulkov, Yong-Bin Kim, Alexander Volkovskii, and Allen Selverston, ""Hybrid Neuronal Architectures for Biomimetic Robot Controller", IEEE International Conference on Robotics and Automation(ICRA) 2006, May 15-19, 2006, Orlando, Florida.
Young Jun Lee, Dae Woon Kang, Jim Doyle, and Y. Kim, "A Sub-1V Power Supply Sub-bandgap with an Extended Voltage and Temperature Range", IEEE International SoC design Conference(ISOCC), October 20-21, 2005, Seoul, South Korea, pp79-82.
J. Ayers, N. Rulkov, Y. Kim, A. Volkovski, and A. Selverston, ``Hybrid Neuronal Architectures for Biomimetic Robot Controllers'', SfN(Society for Neuro Science), November 12-16, 2005, Washington DC, program number 753.18
Rui Tang, Y.B. Kim, ``A Novel Delay Balancing Algorithm for Wave Pipelined Circuits'', IEEE International Symposium on Circuits and Systems(MWSCAS), August 7-10, 2005, Cincinnati, OH, pp. 1035-1038.
Rui Tang, Bart McDanniel, Yong-Bin Kim``A Power Optimization Method for SiGe Butterworth Filter Design'', IEEE International Symposium on Circuits and Systems(MWSCAS), August 7-10, 2005, Cincinnati, OH, pp.1633-1636
Young Jun Lee, Jihyun Lee, and Yong-Bin Kim, ``Low Power CMOS Adaptive Electronic Central Pattern Generator Design'', IEEE International Symposium on Circuits and Systems(MWSCAS), August 7-10, 2005, Cincinnati, pp. 1350-1353
Kyungki Kim, J. Hwang, Y.B. Kim, and F. Lombardi, ``On Modeling and Analysis of Jitter in ATE Using MATLAB'', IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, October 3-5, 2005, pp285-293.
Kyungki Kim, J. Hwang, Y.B. Kim, and F. Lombardi, ``Data Dependent Jitter (DDJ) Characterization Methodology'', IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, October 3-5, 2005, pp294-302.
B.Jang, M. Choi, N.Park, Y. Kim,V. Piuri, F. Lombardi``Spare Line Borrowing Technique for Distributed Memory Cores in SoC'', IEEE IMTC(Instrumentation and Measurement Technology Conference) 2005, Ottawa, Canada, May 16-19 2005, vol.1, pp.43-48
Woo Jin Kim and Y. Kim, ``Wave Pipelined Circuits Synthesis'' IEEE IMTC(Instrumentation and Measurement Technology Conference) 2005, Ottawa, Canada, May 16-19 2005, vol.1, pp.32-46
Duong Tran, Kyong Ki Kim, and Y. Kim, ``Power Estimation in Digital CMOS VLSI Chips'', IEEE IMTC(Instrumentation and Measurement Technology Conference) 2005, Ottawa, Canada, May 16-19 2005, vol.1, pp.317-321
Rui Tang, Fengming Zhang, and Y. Kim, ``Quantum-Dot Cellular Automata SPICE Macro Model'' ACM GLSVLSI'05(Great Lake Symposium on VLSI), Chicago, IL, April 17-19 2005, pp108-111
Daw Woon Kang, Y. Kim, J. Doyle, Mark Hartman, Sandeep Dhar, Marty B. Dermody, Robert C. Woolf, Ravindra S. Ambatipud, ``A Low Powered Methodology for Portable Electronics '',International Symposium of Advanced Radio Technologies, March 1-3 2005, Denver CO, pp.109-116
T. Feng, N. Park, Y. Kim, F. Lombardi, and F. Meyer, ``Reliability Modeling and Assurance of Clockless Wave Pipeline'', IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cannes, France, October 10-13 2004, pp.442-450.
T. Feng, B. Jin, J. Wang, N. Park, Y.B. Kim, and F. Lombardi,``Fault Tolerant Clockless Wave Pipeline Design'' ACM Conference on Computing Fronteers(CF), May 2004, Ischia, Italy, pp.350-356
F. Zhang, R. Tang , and Y. B. Kim, "SET-Based Nano-Circuit Simulation and Design Method Using HSPICE", IEEE GLSVLSI(Great Lake VLSI Symposium) April 2004, Boston, MA, pp.344-34
Y.J.Lee, Jihyun Lee, Y.B. Kim, J. Ayers, ``Low Power Real Time Electronic Neuron VLSI Design Using Sub-threshold Technique'', IEEE International Symposium on Circuits and Systems(ISCAS), May 23-26, 2004, British Columbia, Canada, Vol IV, pp.744-747
J. H. Lee, Y. J. Lee and Y. B. Kim, ``SRAM Word-oriented Redundancy Methodology using Built In Self-Repair'' IEEE ASIC/SoC Conference, Sep 12-15, 2004,
Y. J. Lee, J. H. Lee, J. Y. Heo, F. Zhang and Y. B. Kim, ``Test Methodology for Low Power VLSI Neural Oscillator Circuit'', IMTC 2004 IEEE Instrumentation and Measurement Technology Conference, May 18-20, 2004, Como, Italy, pp.1546-1550
Y. J. Lee, N. Park and Y. B. Kim, ``Timing Requirement for Reliable Latch Based Circuit'', IMTC 2004 IEEE Instrumentation and Measurement Technology Conference, May 18-20,2004,
Ottavi and Y.B.Kim, ``Yield Estimation Method of SRAM Array'', IMTC 2004 IEEE Instrumentation and Measurement Technology Conference, May 18-20,2004,
L. Schiano, M. Momenzadeh, F.Zhang, Y. J. Lee, Y. B. Kim, F. J. Meyer, F. Lombardi, S. Max, "Frequency Domain Measurement of Timing Jitter in ATE", 2004 IEEE Instrumentation and Measurement Technology Conference, May 18-20 2004, Como, Italy, pp.2150-2155
L. Shiano, Y. Kim, F. Lombardi, ``Scan Test IP Cores in an ATE Environment'', IEEE Electronic, Design, Test, and Application(Delta) Conference, Jan 28-30, 2004,
Woo Jin Kim, and Y.B. Kim, ``Applying Automation to Wave Pipelined Circuits'', IEEE GLVLSIS(
Young Joon Lee and Y. Kim, "A Fast and Precise Estimation Method of Crosstalk Noise", IEEE International Symposium on Circuits and Systems(ISCAS),), May 23-26, 2004,
B. Jin, T. Feng, N. Park, K.M. George, F. Lombardi, Y.B. Kim, `` Off-Device Falut Tolerance for Digital Imaging Devices'', IMTC(IEEE Instrumentation and Measurement Technology Conference), May 18-20, 2004,
Woo Jin Kim and Y. Kim, ``Automating the Design Approach to Wave Pipelined Circuits'', IEEE Design and Test of Computers'', Nov/Dec 2003, pp.51-58
Soha Hassoun, Y. Kim, and F. Lombardi, ``Introduction: Clockless Digital VLSI Circuit'', IEEE Design and Test of Computers'', Nov/Dec 2003, pp.5-8
F.-M. Zhang, Y.-J. Lee, T. Kane, L. Schiano, M. Momenzadeh, Y. Kim, F. J. Meyer, F. Lombardi, S. Max, P. Perkins, ``A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment'', IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT'03), Nov.3-5, 2003 Cambridge, MA, USA, pp.159-166
T.Feng, N. Park, Yong-Bin Kim, V.Piuri, ``Yield Modeling and Analysis of A Clockless Asynchronous Wave Pipeline with Pulse Faults'',IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT'03), Nov.3-5, 2003 Cambridge, MA, USA, pp.34-41
Woo Jin Kim, and Y. Kim, 'Clocking for Correct Functionality on Wave Pipelined Circuits'', IEEE International ASIC/SOC Conference 2003,
T. Doyle, Wilsch, Young Jun Lee, and Y.Kim, ``Implementation of 1V Supply Voltage CMOS Subbandgap Reference Circuit '', IEEE International ASIC/SOC Conference, Sep 17-20, 2003
M. Choi, N. park, F. Lombardi, Y. Kim, V. Piuri, ``Optimal Spare Utilization in Repairable and Reliable Memory Cores'', 2003 IEEE International Workshop on Memory Technology, Design and Testing(MTDT-03), July 28-29, 2003,
James T. Doyle, Young Jun Lee, Yong-Bin Kim, ``An Accurate DAC Modeling Technique Based on Wavelet theory'' IEEE Custom Integrated Circuit Conference(CICC) Sep. , 2003,
Yeshwant Kolla, Y.Kim, John Carter, ''A Novel 32-bit Scalable Multiplier Architecture'', Great Lake Symposium on VLSI, April 28-29, 2003,
B. Jin, Park, Y. Kim, Lombardi, ``Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems'', IEEE International Symposium on Network Computing and Applications(NCA-03), April 16-18, 2003, Cambridge, Boston, MA, USA, pp.341-348
Choi, Pottinger, and Y. Kim, ``Need for Undergraduate and Graduate-Level Education in Testing of Microelectronic Circuits and Systems", IEEE 2003 International Conference on Microelectronic Systems Education, June 2003, Los Angeles, CA, U.S.A., pp.121-122
M. Choi, N. Park, V. Piuri, Y.B. Kim and F. Lombardi, ``Evaluating the Repair of System on Chip(SoC) Instrumentation Using Connectivity'', IEEE IMTC(Instrumentation and Measurement Technology Conference), May 20-22, 2003,
F. Karimi, Y.B. Kim, F. Lombardi and N. Park, ``Compression of Partially Specified Test Vectors in an ATE Environment'', IEEE IMTC(Instrumentation and Measurement Technology Conference), May 20-22, 2003,
N. Park, M. Choi, Y.Kim, ``Soft Test/Repair of CCD-based Digital X-ray Instrumentation'', IEEE IMTC(Instrumentation and Measurement Technology Conference), May 20-22, 2003,
Young Jun Lee and Y.Kim, "A Novel Clocking Strategy for Dynamic Circuits", IEEE International Symposium on Quality Electronic Design(ISQED) Conference March 16-20, 2003,
M. Choi, N. Park, Y. Kim, Lombardi, "Hardware/Software Co-Reliability Design in Configurable MCM", 2002 Pacific Rim International Symposium on Dependable Computing (PRDC2002), Tsukuba, Japan, Dec. 16-18, 2002., pp.67-71
Hashempour and Y.Kim, "A Test Vector Generation Methodology For Crosstalk Noise Faults", 2002 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT'02) Conference, Vancouver, Canada, November, 2002, pp.40-47
M. Choi, N. Park, Y. Kim, Lombardi, "Balanced Redundancy Utilization for Dependable Embedded Memory System Core", 2002 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT'02) Conference, Vancouver, Canada, November, 2002, pp.419-427.
Dae Woon Kang and Y.Kim, "Design of Enhanced Differential Cascode Voltage Switch Logic(EDVSL) Circuits for High performance fan-In gate", IEEE International ASIC/SOC Conference 2002, pp.309-313,
Dae Woon Kang and Y. Kim, "Design Flow of Robust Routed Power Distribution for Low Power ASIC",'02 May. ISCAS,
Y. Kim, et al, "Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS", Advanced Research in VLSI Conference, pp 132-147, March 2001, Salt Lake City, Uath, U.S.A. pp.132-147
Y. Kim, et al, "A Digital Trim-Controlled OP Amp. Compensation Technique", IEEE Midwest Symposium on Circuits and Systems 2001, August 2001,
Y.Kim, et al, "A Digital Trim-Controlled On-Chip RC Oscillator", IEEE Midwest Symposium on Circuits and Systems 2001, August 2001, Fairborn, OH, USA, pp.882-885.
Dae-Woon Kang, Y. Kim, "A Deep Sub-Micron SRAM Cell Bistable Analysis Methodology", IEEE Midwest Symposium on Circuits and Systems 2001, August 2001, Fairborn, OH, USA, pp.858-861.
Shivakumar Sompur, Y.B. Kim, "An Investigation into Adiabatic Circuits", IEEE Midwest Symposium on Circuits and Systems 2001, August 2001, Fairborn, OH, USA, pp.294-297
Woo-Jin Kim, Y. Kim, "A Localized Self Resetting Gate Design Methodology", IEEE Midwest Symposium on Circuits and Systems 2001, August 2001, Fairborn, OH, USA, pp.305-308
Y.Kim, T. Chen, "A CMOS Delay Locked Loop(DLL) for Reducing Clock Skew to Under 500pS", '97 Jan. Asia and South Pacific Design Automation Conference,
Y.Kim, T. Chen, "0.65\mu$m CMOS Programmable DLL for DRAM/Logic Merged System", '96 May. ISCAS,
Y.Kim, T. Chen, "Clock Skew on DRAM/Logic Merged Technology Based Systems", '96 May. ISCAS,
Y.Kim, T. Chen, "Assessing Merged DRAM/Logic Technology",'96 May. ISCAS Atlanta, Georgia,
Y.Kim, T. Chen, "On System Level Performance of DRAM/Logic Merged Technology", International Technical Conference on Circuits, Systems, Computers and Comminications, Seoul, Korea, pp.991-994, July 1996.
Y.Kim, T. Chen, "0.8mu$m CMOS Optical Clock Receiver Design", '95 Dec. International Conference on Microelectronics, Kuala Lumpur, Malaysia, pp.37-40
Y.Kim, William N. Carr, "CMOS Sensor Interface for a Robotics LAN", '89 June. UGIM Conference, Amherst, Massachusetts,USA, pp.265-267
Y.Kim, "CMOS PCM COMBO Integrated Circuit Design including Input Offset Compensation Technique for Comparator",'85 KIEE,Seoul,Korea
Y.Kim, "VTR Color AFC Integrated Circuit Design",'83 KIEE Conference,Seoul, Korea
Report
High Performance and Low Power ASIC Design Methodology
(Focusing on Design For Testability)