Publications

2007

2006

2005

2004

JN: Journal Paper

CN: Conference Paper

2010:

C. Tunc, M.B. Tahoori, “Variation Tolerant Logic Mapping for Crossbar Array Nano Architectures”, In IEEE Asian South Pasific Design Automation Conference (ASP-DAC), 2010.

2009:

JN	·	M.B. Tahoori, S. Shazli, “Using Boolean Satisfiability for Computing Soft Error Rates in Early Design Stages”, Elsevier Journal of Microelectronics Reliability, 2009 (in press).
JN	·	M.B. Tahoori, H. Asadi, B. Mullins, D. Kaeli, “Obtaining FPGA Soft Error Rate in High Performance Information Systems”, Elsevier Journal of Microelectronics Reliability, Vol. 49, No. 5, May 2009.
JN	·	M.B. Tahoori, “Low Overhead Defect Tolerance in Crossbar Nano-architectures”, ACM Journal of Emerging Technologies in Computing (JETC), Vol. 5, No. 2, 2009.
CN	·	N. Farazmand, M.B. Tahoori, “Online Multiple Error Detection in Crossbar Nano-architectures”, In IEEE International Conference on Computer Design (ICCD), 2009.
CN	·	A. Abdi, M.B. Tahoori, E. Emamian, “Identification of Critical Molecules Via Fault Diagnosis Engineering”, In International Conference of IEEE Engineering in Medicine and Biology Society, 2009.
CN	·	S. Shazli, M.B. Tahoori, “Soft error rate computation in early design stages using boolean satisfiability”, In ACM Great Lakes Symposium on VLSI, Pages 101-104, 2009.
CN	·	M.B. Tahoori, “BISM: built-in self map for hybrid crossbar nano-architectures”, In ACM Great Lakes Symposium on VLSI, Pages 153-156, 2009.
CN	·	N. Farazmand, M.B. Tahoori, “Online Detection of Multiple Faults in Crossbar Nano-architectures Using Dual Rail Implementations”, In IEEE International Symposium on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH), 2009.
CN	·	S. Shazli, M.B. Tahoori, “Transient Error Detection and Recovery in Processor Pipelines”, In 24^th IEEE International Symposium on Defect and Fault Tolerant in VLSI Systems (DFT), 2009.
CN	·	S. Shazli, M.B. Tahoori, “Modeling Availability and Performability in High Performance Information Systems”, In North Atlantic Test Workshop (NATW), 2009.

2008:

JN	·	A. Abdi, M.B. Tahoori, E. Emamian, “Fault Diagnosis Engineering of Digital Circuits Can Identify Vulnerable Molecules in Complex Cellular Pathways”, Science Signaling, vol. 1, no. 42, pp. 48-61, 2008.
CN	·	S. Shazli, M.B. Tahoori, “Obtaining Microprocessor Vulnerability Factor Using Formal Methods”, In 23^rd IEEE International Symposium on Defect and Fault Tolerant in VLSI Systems (DFT), 2008.
CN	·	M.B. Tahoori, “BISM: Built-in Self Map for Crossbar Nano-Architectures”, In Workshop on Dependable and Secure Nanocomputing (DSN), 2008.
CN	·	S. Shazli, M. Abdul-Aziz, M.B. Tahoori, D. Kaeli, “A Field Failure Analysis of Microprocessors used in Information Systems”, In International Workshop on Resilience Assessment and Dependability Benchmarking (DSN), 2008.
CN	·	S. Shazli, M.B. Tahoori, “A Framework based on Boolean Satisfiability for Soft Error Rate Computation in Early Design Stages”, In International Workshop on Resilience Assessment and Dependability Benchmarking (DSN), 2008.
CN	·	S. Shazli, M.B. Tahoori, D. Kaeli, “A Field Analysis of Soft Errors Occurring in Microprocessors used in Information Systems”, In North Atlantic Test Workshop (NATW), 2008.
CN	·	S. Shazli, M. Abdul-Aziz, M.B. Tahoori, D. Kaeli, “A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems”, In IEEE International Test Conference (ITC), 2008.
CN	·	S. Shazli, M.B. Tahoori, “Modeling Availability and Performability in High Performance Information Systems”, In North Atlantic Test Workshop (NATW), 2009.

2007:

H. Asadi, M.B.Tahoori, B. Mullins, D. Kaeli, K. Granlund, “Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems”, Transactions on Nuclear Science (TNS), Volume 54, Number 6, Pages 2714-2726, December 2007.

H. Asadi, M. B. Tahoori, “Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs”, IEEE Transactions on Very Large Scale Integrated Circuits (TVLSI), Volume 15, Number 12, Pages 1320-1331, December 2007.

M. B. Tahoori and S. Mitra, “Application-dependent Delay Testing of FPGAs”, IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), Volume 26, Number 3, Pages 553-563, March 2007.

B. Mullins, H. Asadi, M. B. Tahoori, D. Kaeli, K. Granlund, R. Bauer, S. Romano, “Case Study: Soft Error Rate Analysis in Storage Systems”, In 25th IEEE VLSI Test Symposium (VTS), Pages 256-264, May 2007.

H. Asadi, M. B. Tahoori, C. Tirumurti, “Estimating Error Propagation Probabilities with Bounded Variances”, In 22nd IEEE International Symposium on Defect and Fault Tolerant in VLSI Systems (DFT), Pages 41-49, September 2007.

B. Mullins, H. Asadi, M. B. Tahoori, D. Kaeli, K. Granlund, R. Bauer, S. Romano, “Case Study: Soft Error Rate Analysis in Storage Systems”, In BARC Workshop, pp. 39-40, 2007.

2006:

M.B. Tahoori, “Application-Independent Defect-Tolerance of Reconfigurable Nano-Architectures”, ACM Journal of Emerging Technologies in Computing (JETC), Volume 2, Number 3, Pages 197-218, July 2006.

M.B. Tahoori, “Application-Dependent Testing of FPGAs”, IEEE Transactions on Very Large Scale Integrated Circuits (TVLSI), Volume 14, Number 9, Pages 1024-1033, September 2006.

H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Reducing Data Cache Susceptibility to Soft Errors”, IEEE Transactions on Dependable and Secure Computing (TDSC), Volume 3, Number 4, Pages 353-364, October-December 2006.

M.B. Tahoori, “Application-Independent Defect-Tolerant Crossbar Nano-Architectures”, In IEEE/ACM International Conference on Computer Aided Design (ICCAD), Pages 730-734, November 2006.

H. Asadi, M.B. Tahoori, “Soft Error Derating Computation in Sequential Circuits”, In IEEE/ACM International Conference on Computer Aided Design (ICCAD), Pages 497-501, November 2006.

M. B. Tahoori, S. Mitra, “Test Compression for FPGAs”, In IEEE International Test Conference (ITC), Pages 1-9, October 2006.

H. Asadi, M.B. Tahoori, “Soft Error Hardening for Logic-level Designs”, In IEEE International Symposium on Circuits and Systems (ISCAS), May 2006.

H. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli “Vulnerability Analysis of L2 Cache Elements to Single Event Upsets”, In Design, Automation and Test in Europe (DATE) Conference, Volume 1, Pages 1-6, March 2006.

H. Asadi and M.B. Tahoori, “Timing-Logic Derating Computation Using Event Propagation Probabilities” In Workshop on System Effects of Logic Soft Errors (SELSE), Pages 1-6, 2006.

2005:

M.B. Tahoori, J. Huang, M. Momenzadeh and F. Lombardi, “Characterization, Test and Logic Synthesis of And-Or-Inv (AOI) Gate Design for QCA Implementation”, IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), Volume 24, Number 12, Pages 1881-1893, December 2005.

J. Huang, M.B. Tahoori, and F. Lombardi, “On the Evaluation of Scaling of QCA Devices in the Presence of Defects at Manufacturing”, IEEE Transactions on Nanotechnology (TNANO), Volume 4, Number 6, Pages 740-743, November 2005.

J. Huang, M.B. Tahoori, and F. Lombardi, “Fault-Tolerance of Switch Blocks and Switch Block Arrays in FPGA”, IEEE Transactions on Very Large Scale Integrated Circuits (TVLSI), Volume 13, Number 7, Pages 794-807, July 2005.

I. R. Bahar, M. B. Tahoori, S. K. Shukla and F. Lombardi, “Guest Editors’ Introduction: Challenges for Reliable Design at the Nanoscale”, IEEE Design and Test of Computers, Volume 22, Number 4, Pages 295-297, July-August 2005.

M. B. Tahoori, S.Mitra, “Application-Independent Testing of FPGA Interconnects” In IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), Volume 24, Number 11, Pages 1774-1783, November 2005.

J. Huang, M.B.Tahoori, and F. Lombardi, “Probabilistic Analysis of Fault Tolerance for Switch Block Array in FPGAs” In International Journal of Embedded Systems (JES), Volume 1, Number 3-4, Pages 250-262, 2005.

H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Reliability Tradeoffs in Design of Cache Memories,” Workshop on Architectural Reliability (WAR-1), held in conjunction with 38th International Symposium on Microarchitecture (MICRO-38), Barcelona, Spain, Dec. 2005.

H. Asadi and M. B. Tahoori, “Soft Error Modeling and Protection for Sequential Elements”, Proc. of the IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), pp. 463-471, Monterey, CA, Oct. 2005.

G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation in Digital Circuits,” Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 2005.

G. Asadi and M. B. Tahoori, “Soft Error Mitigation for SRAM-Based FPGAs,” Proc. of the 23^rd IEEE VLSI Test Symposium (VTS05), Palm Springs, CA, May 2005.

G. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Reliability and Performance in the Memory Hierarchy,” Proc. of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS05), Austin, Texas, March 2005.

G. Asadi and M. B. Tahoori, “An Accurate SER Estimation Method Based on Propagation Probability,” Proc. of the IEEE Design, Automation and Test in Europe Conference (DATE’05), March 2005.

G.. Asadi and M. B. Tahoori, “Soft Error Rate Estimation and Mitigation for SRAM-Based FPGAs,” Proc. of the 13^th ACM International Symposium on Field-Programmable Gate Arrays (FPGA-2005) , Monterey, CA, Feb. 2005.

2004:

JN	·	M. B. Tahoori, S. Mitra, “Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configuration,” In IEEE Transaction on Computer Aided Design of Integrated Circuits, February 2004.
CN	·	X. Wang, M. Ottavi, F. Lombardi, “Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs.”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004 , Cannes, France, October 2004
CN	·	X. Wang, M. Ottavi, F. Meyer, F. Lombardi, “On The Yield of Compiler-based eSRAMs”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, Cannes, France, October 2004
CN	·	G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs,” Proc. of the MAPLD04 Conference, Washington DC, September 2004.
CN	·	J. Huang, M. B. Tahoori, F. Lombardi, “Routability and Fault Tolerance of FPGA Interconnect Architectures,” In International Test Conference, 2004.
CN	·	J. Huang, M. Momenzadeh, M. B. Tahoori, F. Lombardi, “Defect Characterization for Scaling of QCA Devices,” In IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004.
CN	·	L. Schiano, M. Ottavi, F. Lombardi, “Markov Models of Fault-Tolerant Memory Systems Under SEU”, IEEE International Workshop on Memory Technology, Design and Testing , San Jose, CA, August 2004
CN	·	J. Huang, M. B. Tahoori, F. Lombardi, “On the Defect Tolerance of Nano-scale Two-Dimensional Crossbars,” In IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004.
CN	·	J. Huang, M. Momenzadeh, M.B. Tahoori, and F. Lombardi, “Design and Characterization of An And-Or-Inverter (AOI) Gate for QCA Implementation”, In Great Lake Symposium on VLSI (GLSVLSI), 2004.
CN	·	M. Momenzadeh, M.B. Tahoori, J. Huang, and F. Lombardi, “Quantum Cellular Automata: New Defects and Faults for New Devices”, In Fault Tolerance in Parallel and Distributed Systems (FTPDS) Workshop, 2004.
CN	·	M.B. Tahoori, J. Huang, M. Momenzadeh and F. Lombardi, “Defects and Faults in Quantum Cellular Automata at Nano Scale”, In 22^nd VLSI Test Symposium, 2004.
CN	·	J. Huang, M.B. Tahoori, and F. Lombardi, “Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array”, In Reconfigurable Architectures Workshop, 2004.
CN	·	M. B. Tahoori, S. Mitra, “Fault Detection and Diagnosis Techniques for Molecular Computing”, In NanoTech, 2004.
CN	·	M.B. Tahoori, J. Huang, M. Momenzadeh and F. Lombardi, “Defect and Fault Characterization in Quantum Cellular Automata”, In NanoTech, 2004.
CN	·	R. Murgai, M. B. Tahoori, S. Reddy, T. Miyoshi, T. Hiore, “Sensitivity-Based Modeling and Methodologies for Full-Chip Substrate Noise Analysis,” In Design Automation and Test in Europe (DATE) Conference, 2004.
CN	·	M. B. Tahoori, F. Lombardi, “Testing of Quantum Dot Cellular Automata Based Designs”, In Design Automation and Test in Europe (DATE) Conference, 2004.
CN	·	J. Huang, M.B. Tahoori, and F. Lombardi, “Fault Tolerance of Programmable Switch Blocks”, In Design Automation and Test in Europe (DATE) Conference, 2004.