Research: Fault and Variation Tolerant Asynchronous Architecture Applicable for Crossbar Arrays

Current semiconductor technology is going to face fundamental barriers in continuation of Moore's law. Fundamental physical issues and increasing costs associated with lithography fabrication are major obstacles for increasing device density and reducing device feature size. Nanoelectronics is an alternative for current CMOS technology to overcome physical barriers as well as increased fabrication costs. Fabricated devices and architectures based on nanostructures, in particular Carbon NanoTube (CNT) and NanoWires (NW), show effectiveness of this technology as alternative among other technologies.

Fundamental electronic devices such as diode, FET, and memory element have been assembled from well-defined nanoscale building blocks e.g. CNTs, SiNWs and molecules. Proposed device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Generally CNTs and SiNWs can be aligned in one direction, and this geometry restriction leads to crossbar arrays as feasible structure to integrate devices. Special molecules (e.g. Rotaxane) are used between crossed lines in the crosspoints to have programmability nature for interconnect and logic implementation.

The main feature of this emerging nanotechnology is its bottom-up non-lithographic fabrication process which can remove the limit of lithography in terms of feature size and cost. However, inability to control whether NTs are semiconducting or metallic as well as poor control on doping density of SiNWs poses a serious challenge in this technology. Atomic device size, sensitivity of electrical characteristics at this scale, and nature of fabrication process pose major issues for nanoelectronics in the form of extreme parameter variation and high failure rate. 

Extreme parameter variation in this nanotechnology leads to difficulties in delay control and prediction as well as difficulties in global clock routing.  Therefore, using conventional synchronous methodologies are inefficient to design and implement sequential logics in this emerging technology. Asynchronous methodologies with minimum timing assumptions seem as a promising alternative to overcome extreme variation issues.  High failure rate makes it possible to have multiple faults in the circuit. Therefore, the methodologies should also be efficient in tolerating multiple faults.  

Asynchronous design represents an alternative to synchronous design for sequential logic implementation. In an asynchronous circuit the clocking methodology is replaced by some form of handshaking between neighboring registers, replacing the global clock signal with local request and acknowledges signaling.

It has been proposed verity of asynchronous methodologies based on CMOS technology features and constraints.  Among all these methodologies, delay-insensitive (DI) circuits are inherently robust against any delay variations. On the other hand, unfortunately it is proved that class of circuits which can be designed as DI is limited to small set of circuits implemented by only C-element and inverter gates. By introducing delay constraint on some wires of DI circuits, Quasi Delay-Insensitive (QDI) circuits have been proposed which makes it possible to implement any desired circuit. Wires with delay constraint on them are named isochronic forks, which require careful implementation for correct functionality. Predictability and controllability of delay in CMOS technology make it easy to meet isochronic forks constraint of QDI circuits.  As mentioned earlier, nanoelectronics suffers from extreme delay variation which makes it impractical to use QDI circuits without special cares.

Our goal in this research is investigating asynchronous circuits to sequential logic implementation. In this research we are trying to introduce an asynchronous architecture with minimum trimming assumption. However, this architecture should be efficient in toleration multiple faults at the same time.