Fig. 1. A basic example for a nano crossbar. In the example, the diodes show activated junctions that behave as a diode and where there is no diode shown, the junctions are deactivated.
Research: Variation and Defect Tolerant Mapping for Crossbar based Nano Architectures
Due to extreme scaling in current CMOS technology as Moore's Law suggested, some problems due to quantum effects as well as manufacturing methods have been rising. Some of these problems are power dissipation, parasitic issues, direct tunneling, etc. Moreover, the manufacturing tools for smaller lithography is getting more expensive and too complex. Even though the semiconductor industry has overcome with the similar issues so far, the issues get more complicated. However, using bottom-up approach, emerging technologies with nanowires and Carbon nanotubes could be used for more scaling down.
Among the alternative technologies, nanowires seem to be more promising since they can be easily doped with Silicon, Germanium, etc. Using nanowires, interconnections, p-n-diode rectifiers by doping with Silicon, FETs, and logic gates have been presented. Since the emerging structures are very regular in structure, they well suited to the implementation of PLAs and FPGAs. These regular structures are used for the manufacturing of nano crossbars which are the main building blocks for nano architectures. Nano crossbars are implemented using two perpendicular nanowires where at each intersection, there exists a programmable molecular switch that can be turned 'on' or 'off' by applying appropriate voltage. The nano crossbar structures have been used for the logic function for the nano architectures like CMOL, nanoPLA, NanoFabrics, etc.
Fig. 1. A basic example for a nano crossbar. In the example, the diodes show activated junctions that behave as a diode and where there is no diode shown, the junctions are deactivated.
Even though, emerging technologies seem promising, defects and variations seem to be the two major problems. Nanowires, that are just a few atom width, can be broken. More than open or shorted nanowires, the switches at the crosspoints may be defective as well. The switches may be stuck-open where they cannot be activated or stuck-closed where they cannot be deactivated. Moreover, due to statistical assembly process, the variations are considered huge. Due to low controllability, resistances, capacitances, etc. result in huge variations.
We aim minimizing variations which can be considered as delay differences. We use a lumped modeling where the variation (i.e. delay) of crosspoints, wires, connections are lumped into the crosspoint variations. In this study, we focus on not only variation minimization, but also defect tolerant mappings.
For variation optimization and defect tolerance for the crossbars, we use the reconfigurability and the interchangeability features while mapping the logic functions. Since there are different mappings for a crossbar, we try to find the best that results in minimum variation. Currently, we try to reduce the variation cost with two approaches: Offline Mapping and On-the-fly Mapping using appropriate characterization (delay) testing methods. Since it would be intractable to apply exhaustive methods, we propose both heuristic methods and greedy methods to find a defect free cost optimized mapping. The results show that the proposed techniques are effective.
Currently, we are also working on the optimization and defect tolerance of crossbar arrays. Crossbar arrays are a set of cascaded crossbars where (i)th crossbar outputs are directly connected to (i+1)th crossbar inputs. Therefore, for any change at the outputs of the (i)th crossbar, the inputs of the (i+1)th crossbar will change which results in less flexibility.
Fig. 2. Nano crossbar arrays are formed of cascaded nano crossbars.