Past Seminars

Fall 2004

· Oct 26: Luca, “Performance Characterization of Memory System Using Markov Model”

· Oct 19: Mariam, “Defect Characterization for Scaling of QCA Devices”

· Oct 12: Hossein, “Balancing Reliability and Performance in the Memory Hierarchy”

· Oct 5: Marco, “Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs”

· Sep 28: Marco, “On The Yield of Compiler-based eSRAMs”

· Sep 21: Jing, “Routability and Fault Tolerance of FPGA Interconnect Architectures”

Summer 2004

· August 11: Pedram: “Programming Language Interface (PLI) ”

· August 4: Marco: “Design of a QCA Memory with Parallel Read/Serial Write”

· July 28: Luca: “Markov Models of Fault-Tolerant Memory Systems Under SEU ”

· July 21: Bhushan, “Test Generation for Multiple-output Propagation Transition Faults using Boolean Satisfiability”

· July 14: Luca, “Test Data Compression ”

· July 7: Jing, “QCA Scaling with Bistable Engine and Coherence Vector engine”

· June 30: Vamsi, “Memory Architectures for QCA”

· June 23: Hossein, “An Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs”

Spring 2004

· Pedram Riahi, “Intellectual Property (IP) Core-based System-on-Chip (SoC) testing using Hardware Description Languages' (HDLs) Procedural Language Interface (PLI)”

· Luca Schiano, "Methodologies and Instrumentation for EMI Induced jitter measurements in an ATE”

· Huang Jing, "Design and Test of Fault Tolerant Quantum dot Cellular Automata”

· Mariam Momenzadeh , “Defects and Fault Characterization in Quantum Cellular Automata”

· Vamsi Vankamamidi, “QCA based Interconnection networks, analysis and timing”

· Hossein Asadi, “System Level Soft Error Rate Estimation”

· Bhushan Vaida, Intellectual Property (IP) Core-based System-on-Chip (SoC) testing using Hardware Description Languages' (HDLs) Procedural Language Interface (PLI)