Invited Speaker

Low Power Digital Adaptable Voltage Controller Based on Hybrid Control and and Reverse Phase Mode, National Semiconductor Company, Longmont CO, USA, August 2004

Low Power Digital Adaptable Voltage Controller Based on Hybrid Control and and Reverse Phase Mode, Busan University, Busan, Korea, June 2003

Power Saving Techniques for TFT LCD Controller Chip Design, Samsung Electronics, June 2003

High Speed Full Custom VLSI Design Tutorial and Interconnect Related Clock/Power Issue, IC Design Education Center(IDEC), Seoul, South Korea, 2002

VLSI Circuit Design Reliabilty Tutorial, SeoDu InChip, Seoul, South Korea, 2002

Clock and Power Distribution for DRAM/Logic Merged VLSI Systems, Hewlett Packard Lab, Palo Alto, 1999

High Performance VLSI Circuit Design Methodology, Korean Advanced Institute of Science and Technology(KAIST), 1998 Samsung Advanced Institute of Technology, 1998

Power Supply IR Drop Analysis Methodology for High Performance, Johns Hopkins University, Baltimore, MD, 1998

Clock Signal Distribution for a High Performance Microprocessor, Colorado State University, Fort Collins, CO, 1997

VLSI Systems Design Using DRAM/Logic Merged Technology, Lucent Technology(Bell Lab Innovations), Murray Hill, New Jersey, 1997

High Performance VLSI Circuit Design Methodology, Samsung Advanced Institute of Technology, Kiheung, Korea, 1998

Closk Skew Analysis Methodology for GHz Level Microprocessor, Korean Advanced Institute of Science and Technology, Daejon, Korea, 1998

Deep Sub-Micron Design Methodolgy and Issues, San Jose State University, San Jose, California, 1997

DRAM/Logic Merged Design Technology and Its Applications, Samsung Electronics Comapany, Seoul Korea, 1996

Intel P6(Pentium Pro) Floating Point Execution Unit design, Samsung Electronics Company, Seoul, korea, 1994