Substrate
Noise Analysis for Mixed-Signal VLSI Designs
Mixed-signal
designs have become ubiquitous with the proliferation of deep sub-micron (DSM)
system-on-chip (SOC) design methodologies.
In such systems, maintaining signal integrity and reducing noise have
become the most vexing issues. Switching
noise due to large signal swings in the digital part can propagate through the
common substrate and corrupt sensitive analog part (See figure below).
In
technologies that have low resistivity substrates, noise generated in one
region of the die may cause the rest of the chip to malfunction.
Decreasing
feature size lets more devices to be packed on a chip, generating higher
overall noise. In addition, smaller
device geometries translate to reduced threshold voltages resulting in higher
sub-threshold leakage currents. Smaller
devices are also more sensitive to noise because of reduced noise margins.
With
increasing design complexity, it is not possible to simulate for SN with a
detailed SPICE model that uses an accurate model for each transistor. The
increasing switching rates and decreasing transition times are also responsible
for more transients. Due to all these
DSM effects, substrate noise analysis
(SNA) has become a critical problem in most mixed-signal designs.
· R. Murgai, S. Reddy, T.
Miyoshi, T. Hiore, M. B. Tahoori, “Sensitivity-Based
Modeling and Methodologies for Full-Chip Substrate Noise Analysis,” In
Design Automation and Test in Europe (DATE) Conference, 2004.