PUBLICATIONS

Journal Papers

·       M.B. Tahoori, “Application-Independent Defect-Tolerance of Reconfigurable Nano-Architectures”, in ACM Journal of Emerging Technologies in Computing (JETC), 2006.

·       M.B. Tahoori, “Application-Dependent Testing of FPGAs”, in IEEE Transaction on Very Large Scale Integrated Circuits (TVLSI), 2006.

·       G. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli, “Reducing Data Cache Susceptibility to Soft Errors”, In IEEE Transactions on Dependable and Secure Computing, 2006.

·       M. B. Tahoori, S. Mitra, “Application-Dependent Delay Testing of FPGAs,” In IEEE Transaction on Computer Aided Design of Integrated Circuits, 2006.

·       I. R. Bahar, M. B. Tahoori, S. K. Shukla, and F. Lombardi, “Guest Editors’ Introduction: Challenges for Reliable Design at the Nanoscale”, IEEE Design and Test of Computers, April 2005.

·       M. Momenzadeh, J. Huang, M.B. Tahoori, and F. Lombardi, “On the Evaluation of Scaling of QCA Devices in the Presence of Defects at Manufacturing”, in IEEE Transaction on Nanotechnology (TNANO), November 2005.

·       J. Huang, M.B. Tahoori, and F. Lombardi, “Fault-Tolerance of Switch Blocks and Switch Block Arrays in FPGA”, in IEEE Transaction on Very Large Scale Integrated Circuits (TVLSI), July 2005.

·       M.B. Tahoori, J. Huang, M. Momenzadeh and F. Lombardi, “Characterization, Test and Logic Synthesis of And-Or-Inv (AOI) Gate Design for QCA Implementation”, in IEEE Transaction on Computer Aided Design of Integrated Circuits, December 2005.

·       M. B. Tahoori, S. Mitra, “Application-Independent Testing of FPGA Interconnects,” in IEEE Transaction on Computer Aided Design of Integrated Circuits, November 2005.

·       J. Huang, M.B. Tahoori, and F. Lombardi, “A Probabilistic Analysis of Fault Tolerance for Switch Block Array in FPGAs”, In Int’l Journal of Embedded Systems, 2005.

·       M.B. Tahoori, J. Huang, M. Momenzadeh and F. Lombardi, “Testing Quantum Cellular Automata”, IEEE Transaction on Nanotechnology (TNANO), December 2004.

·       M. B. Tahoori, “Application-Specific Bridging Fault Testing of FPGAs” in Journal of Electronic Testing, Theory and Application, June 2004.

·       M. B. Tahoori, S. Mitra, “Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configuration,” In IEEE Transaction on Computer Aided Design of Integrated Circuits, February 2004.

 

Conference and Workshop Papers

·       M.B. Tahoori, “Application-Independent Defect-Tolerant Crossbar Nano-Architectures”, In IEEE International Conference on Computer Aided Design (ICCAD), 2006.

·       G. Asadi, M.B. Tahoori, “Soft Error Derating Computation in Sequential Circuits”, In IEEE International Conference on Computer Aided Design (ICCAD), 2006.

·       M. B. Tahoori, S. Mitra, “Test Compression for FPGAs”, In IEEE International Test Conference (ITC), 2006.

·       G. Asadi, M.B. Tahoori, “Timing-Logic Derating Computation Using Event Propagation Probabilities”, In Workshop on System Effects of Logic Soft Errors (SELSE), 2006.

·       G. Asadi, M.B. Tahoori, “Soft Error Hardening for Logic-Level Designs”, In IEEE International Symposium on Circuits and Systems (ISCAS), 2006.

·       G. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli, “Vulnerability Analysis of L2 Cache Elements to Single Event Upsets”, In Design Automation and Test in Europe (DATE) Conference, 2006.

·       G. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli, “Reliability Tradeoffs in Design of Cache Memories”, In Workshop on Architecture Reliability (WAR), 2006.

·       M.B. Tahoori, “A Mapping Algorithm for Defect Tolerance of Reconfigurable Nano-architectures”, In IEEE International Conference on Computer Aided Design (ICCAD), 2005.

·       M.B. Tahoori, G. Asadi, “Soft Error Modeling and Protection for Sequential Elements”, In IEEE Symposium on Defect and Fault Tolerant (DFT), 2005.

·       M.B. Tahoori, “Defects, Yield, and Design in Sublithographic Nano-electronics”, In IEEE Symposium on Defect and Fault Tolerant (DFT), 2005.

·       B. Vaidya, M.B. Tahoori, “Delay Test Generation with All Reachable Output Propagation and Multiple Excitations”, In IEEE Symposium on Defect and Fault Tolerant (DFT), 2005.

·       J. Kumar, M.B. Tahoori, “A Low Power Soft Error Suppression Technique for Dynamic Logic”, In IEEE Symposium on Defect and Fault Tolerant (DFT), 2005.

·       M.B. Tahoori, “Yield Analysis and Defect Tolerance of Molecular Crossbars”, In IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH), 2005.

·       J. Kumar, M.B. Tahoori, “Use Of Pass Transistor Logic To Minimize The Impact Of Soft Errors In Combinational Circuits”, In Workshop on System Effects of Logic Soft Errors (SELSE), 2005.

·       G. Asadi, M.B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation In Digital Circuits”, In IEEE International Symposium on Circuits and Systems (ISCAS), 2005.

·       G. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli, “Balancing Performance and Reliability in the Memory Hierarchy”, In IEEE Boston Area Architecture (BARC) Workshop, 2005.

·       G. Asadi, M.B. Tahoori, “Soft Error Mitigation for SRAM-based FPGAs”, In VLSI Test Symposium (VTS), 2005.

·       G. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli, “Balancing Performance and Reliability in the Memory Hierarchy”, In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2005.

·       G. Asadi, M.B. Tahoori, “An Accurate SER Estimation Method Based on Propagation Probability”, In Design Automation and Test in Europe (DATE) Conference, 2005.

·       G. Asadi, M.B. Tahoori, “Soft Error Rate Estimation and Mitigation for SRAM-based FPGAs”, In ACM International Conference on Field Programmable Gate Arrays (FPGA), 2005.

·       J. Huang, M.B. Tahoori, and F. Lombardi, “On the Defect Tolerance of Nano-scale Two-Dimensional Crossbars”, In IEEE Symposium on Defect and Fault Tolerant (DFT), 2004.

·       J. Huang, M.B. Tahoori, and F. Lombardi, “Defect Characterization for Scaling of QCA Devices”, In IEEE Symposium on Defect and Fault Tolerant (DFT), 2004.

·       M.B. Tahoori, “Application-Dependent Diagnosis of FPGAs”, In International Test Conference (ITC), 2004.

·       M. B. Tahoori, S. Mitra, “Interconnect Delay Testing of Designs on Programmable Logic Devices”, In International Test Conference (ITC), 2004.

·       J. Huang, M.B. Tahoori, and F. Lombardi, “Routability and Fault Tolerance of FPGA Interconnect Architectures”, In International Test Conference (ITC), 2004.

·       G. Asadi, M.B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation of SRAM-based FPGAs”, In MAPLD International Conference, 2004.

·       M. B. Tahoori, “An Analytical Framework for Soft Error Rate Estimation”, In 22nd VLSI Test Symposium (Elevator Talk), 2004.

·       M. B. Tahoori, S. Mitra, “Toward Testing Reconfigurable Molecular Systems”, In Test Resource Partitioning (TRP) Workshop, 2004.

·       M.B. Tahoori, “Test and Diagnosis of Complex Designs Implemented on FPGAs”, In North Atlantic Test Workshop (NATW), 2004.

·       B. Vaidya, M.B. Tahoori, “Delay Testing Based on Transition Faults Propagated to All Reachable Outputs”, In Current and Defect-Based Testing (DBT) Workshop, 2004.

·       M. B. Tahoori, S. Mitra, “Defect and Fault Tolerance in Reconfigurable Molecular Computing” In Field Custom Computing Machines (FCCM) Conference, 2004.

·       M. B. Tahoori, S. Mitra, “Thorough Delay Testing of Designs on Programmable Logic Devices” In International Test Synthesis Workshop (ITSW), 2004.

·       J. Huang, M. Momenzadeh, M.B. Tahoori, and F. Lombardi, “Design and Characterization of An And-Or-Inverter (AOI) Gate for QCA Implementation”, In Great Lake Symposium on VLSI (GLSVLSI), 2004.

·       M. Momenzadeh, M.B. Tahoori, J. Huang, and F. Lombardi, “Quantum Cellular Automata: New Defects and Faults for New Devices”, In Fault Tolerance in Parallel and Distributed Systems (FTPDS) Workshop, 2004.

·       M.B. Tahoori, E. J. McCluskey, M. Renovell, and P. Faure, “A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs”, In 22nd VLSI Test Symposium, 2004.

·       M.B. Tahoori, J. Huang, M. Momenzadeh and F. Lombardi, “Defects and Faults in Quantum Cellular Automata at Nano Scale”, In 22nd VLSI Test Symposium, 2004.

·       J. Huang, M.B. Tahoori, and F. Lombardi, “Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array”, In Reconfigurable Array Workshop, 2004.

·       M. B. Tahoori, S. Mitra, “Fault Detection and Diagnosis Techniques for Molecular Computing”, In NanoTech, 2004.

·       M.B. Tahoori, J. Huang, M. Momenzadeh and F. Lombardi, “Defect and Fault Characterization in Quantum Cellular Automata”, In NanoTech, 2004.

·       R. Murgai, M. B. Tahoori, S. Reddy, T. Miyoshi, T. Hiore, “Sensitivity-Based Modeling and Methodologies for Full-Chip Substrate Noise Analysis,” In Design Automation and Test in Europe (DATE) Conference, 2004.

·       M. B. Tahoori, F. Lombardi, “Testing of Quantum Dot Cellular Automata Based Designs”, In Design Automation and Test in Europe (DATE) Conference, 2004.

·       J. Huang, M.B. Tahoori, and F. Lombardi, “Fault Tolerance of Programmable Switch Blocks”, In Design Automation and Test in Europe (DATE) Conference, 2004.

·       M. B. Tahoori, “Application-Dependent Testing of FPGA Interconnects,” In IEEE Symposium on Defect and Fault Tolerant (DFT), 2003.

·       M. B. Tahoori, “Testing for Transition Faults Caused by Resistive Shorts in FPGA Interconnects,” In Current and Defect-Based Testing Workshop, 2003.

·       M. B. Tahoori, “Using Satisfiability in Application Dependent Testing of FPGA Interconnects,” In 40th Design Automation Conference, 2003.

·       M. B. Tahoori, S. Mitra, “Automatic Configuration Generation for FPGA Interconnect Testing,” In 21st VLSI Test Symposium, 2003.

·       M. B. Tahoori, “Application-Dependent Testing of FPGAs for Bridging Faults,” In ACM International Conference on Field Programmable Gate Arrays, February 2003.

·       M. B. Tahoori, “A High Resolution Diagnosis Technique for Open and Short Defects in FPGA Interconnects,” In ACM International Conference on Field Programmable Gate Arrays, February 2003.

·       M. B. Tahoori, S. Mitra, S. Toutounchi, E. J. McCluskey, “Fault Grading FPGA Interconnect Test Configuration,” In International Test Conference, October 2002.

·       M. B. Tahoori, “Improving Detectability of Resistive Open Defects in FPGA,” In 5th MAPLD International Conference, September 2002.

·       M. B. Tahoori, “Testing for Resistive Open Defects in FPGAs,” In IEEE International Conference on Field Programmable Technology, December 2002.

·       M. B. Tahoori, "Diagnosis of Open Defects in FPGA Interconnects," In IEEE International Conference on Field Programmable Technology, December 2002.

·       S. Hessabi and M. B. Tahoori, “A Novel Model for Control-Flow Errors in High-Level Test Generation,” In 7th CSI Computer Conference (CSICC 2002), Tehran, Iran, February 2002.

·       M. Ghodsi, M. B. Tahoori, “Mapping of recursive Algorithms to VHDL Systolic Specifications”, In 8th Iranian Electrical Engineering Conference (IEE'2000), Isfahan University of Technology, May 2000.

 

Technical Reports

·       M. B. Tahoori, S. Mitra, E. J. McCluskey, “Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configuration,”CRC-TR 02-1, Stanford University, 2002.

·       M. B. Tahoori, “Techniques for Detection of Resistive Open Defects in FPGAs,” CRC-TR 02-3, Stanford University, 2002.

·       M. B. Tahoori, S. Mitra, “Automatic Configuration Generation for Interconnect Testing in Switch-Based FPGAs,” CRC-TR 02-2, Stanford University, 2002.

·       M. B. Tahoori, “Application-Dependent Testing of FPGA Interconnects,” CRC-TR 02-4, Stanford University, 2002.

 

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