Mehdi B. Tahoori
Associate
Professor
Department of Electrical and Computer
Engineering
Research:
Dependable Nano-Computing Lab (DNL) at
Northeastern University
Broadly, I am interested in test, reliability, and
design automation of digital systems. In particular, my current research
directions are as follows:
- Design and test
automation, defect and fault tolerance in emerging nanotechnologies
1. Crossbar array
nano-architectures
2.
Quantum-dot cellular
automata (QCA)
- Dependable Computing
- Defect and Fault
tolerant computing
- Soft error reliability
modeling and mitigation
- Software Reliability
- Testing aspects of
computer systems, test generation algorithms and design for testability
- Reconfigurable
computing
- Modeling, estimation and tolerance of noise in
mixed-signal SoCs
- Computer-Aided Design
(CAD) of VLSI
- System Biology
- Analysis of complex
molecular pathways in human disorders
Publications:
·
Unified list of publications
·
Link to some of my papers and presentations on FPGA
Testing at Stanford CRC.
Professional
Organizations:
·
Program
Chair of IEEE Defect
Based Testing (DBT) Workshop at VTS 2005, 2006.
·
Program Committee Member of IEEE International Workshop on Design and Test
of Defect-Tolerant Nanoscale Architectures (NANOARCH) 2005, 2007.
·
Program Committee Member of IEEE International Test Synthesis Workshop (ITSW)
2005-2008.
·
Program Committee Member of IEEE North Atlantic Test
Workshop (NATW) 2005-2008.
·
Guest Editor of IEEE
Design & Test Special Issue on “Advanced Technologies
and Reliable Design for Nanotechnology Systems”, 2005.
Teaching:
(Most
Recent)
·
Fall 2008:
ECE U324: Computer Architecture and Organization
(Undergraduate)
·
Spring 2008:
ECE G339: Testing and Design-for-Testability
(Graduate)
ECE U324: Computer Architecture and Organization
(Undergraduate)
·
Fall 2007:
ECE U324: Computer Architecture and Organization
(Undergraduate)
·
Fall 2006:
ECE G339: Testing and Design-for-Testability
(Graduate)
·
Spring 2006:
ECE U528: CAD for Design and Test (Undergraduate)
Education:
- I
received my Ph.D. from the Department
of Electrical Engineering at Stanford
University in June 2003. I was working in Center for Reliable Computing (CRC)
under supervision of Professor
Edward J. McCluskey. My thesis topic was “Testing
FPGAs” .
- I
received my M.S. degree in Electrical Engineering (Computer Systems) from
- I
received my B.S. Double Major in Computer Engineering and Computer Science
(with Honors) from the Department
of Computer Engineering at Sharif
University of Technology,
Patents:
·
H. Asadi, K. Granlund, M. B. Tahoori, D. Kaeli,
“Analytical Soft Error Evaluation
Tool for SRAM-Based FPGAs”, Joint Patent Application by EMC
Corporation and Northeastern University, January 2008.
·
A. Abdi, M. B. Tahoori, “Systems and Methods for Fault Diagnosis in Molecular Networks”,
Joint Patent Application by Northeastern University and New Jersey Institute of
Technology, International Patent Application Number: PCT/US08/054674, US Patent
Application Number 60/902,767, February 2008 (patent pending).
·
R. Murgai, S. Reddy, T. Miyoshi, T. Horie, M. B. Tahoori,
“Analyzing Substrate Noise”,
·
M. B. Tahoori,
Contact Information:
307 Dana Research
Building
Dept of ECE
Northeastern University
Phone: (617) 373-2032
Fax: (617) 373-8970
Email: mtahoori@ece.neu.edu