Waleed M. Meleis


Associate Professor

Department of Electrical and Computer Engineering
409 Dana Research Center
Northeastern University
360 Huntington Avenue
Boston MA 02115-5000

Office: 320 Dana Research Center

617-373-8970 (fax)



Information for students

Research

Curriculum vita


Education


Funding


Journal articles

  1. M. Fayyazi, D. Kaeli and W. Meleis, An adjustable linear-time parallel algorithm for maximum weight bipartite matching, Information Processing Letters, Vol. 97, No. 5, March 2006, pp. 186-190.
  2. F. Karimi, Z. Navabi, W. Meleis, and F. Lombardi, Using Data Compression in Automatic Test Equipment for System-on-Chip Testing, IEEE Transactions on Instrumentation and Measurement, Vol. 53, No. 2, April 2004, pp. 308-317.
  3. I. Baev, W. Meleis, S. Abraham, Backtracking-based Instruction Scheduling To Fill Branch Delay Slots, International Journal on Parallel Programming, Vol. 30, December 2002, pp. 397-418.
  4. I. Baev, W. Meleis, and A. Eichenberger, Lower Bounds on Precedence-Constrained Scheduling for Parallel Processors, Information Processing Letters, Vol. 83, No. 1, July 2002, pp. 27-32.
  5. I. Baev, W. Meleis, and A. Eichenberger, An Experimental Study of Algorithms for Total Weighted Completion Time Scheduling, Algorithmica, Vol. 33, No. 1, May 2002, pp. 34-51.
  6. M. Ashouei, D. Jiang, W. Meleis, D. Kaeli, M. El-Shenawee, E. Mizan, Y. Wang and C. Rappaport, Profile-based Characterization and Tuning for Subsurface Sensing and Imaging Applications, International Journal of SIMULATION: Systems, Science and Technology, Vol. 3, No. 1-2, June 2002, pp. 40-55.
  7. M. El-Shenawee, C. Rappaport, D. Jiang, and W. Meleis, Electromagnetics Computations Using the MPI Parallel Implementation of the Steepest Descent Fast Multipole Method (SDFMM), Applied Computational Electromagnetics Society Journal, Vol. 17, 2002, pp. 112-122.
  8. D. Jiang, W. Meleis, M. El-Shenawee, E. Mizan, M. Ashouei, and C. Rappaport, Parallel Implementation of the Steepest Descent Fast Multipole Method (SDFMM) On a Beowulf Cluster for Subsurface Sensing Applications, IEEE Microwave and Wireless Components Letters, Vol. 12, No. 1, January 2002, pp. 24-26.
  9. W. Meleis, A. Eichenberger, and I. Baev, Scheduling Superblocks with Bound-based Branch Tradeoffs, IEEE Trans. on Computers, Vol. 50, No. 8, August 2001, pp. 784-797.
  10. W. Meleis, Dual-Issue Scheduling for Binary Trees with Spills and Pipelined Loads, SIAM Journal on Computing, Vol. 30, No. 6, 2001, pp. 1921-1941.
  11. J. Kalamatianos, A. Khalafi, D. Kaeli, and W. Meleis, Temporal-based Cache Interaction for Improved Program Layout, IEEE Trans. on Computers, Special Issue on Cache Memory, 1999, pp. 168-175.
  12. J. Kalamatianos, A. Khalafi, D. Kaeli, B. Calder, and W. Meleis, Program Reordering Using Estimated Call Graphs, DEC Technical Journal, Special Issue on Programming Languages and Tools, accepted 1999.
  13. M. Leeser, W. Meleis, M. Vai, S. Chiricescu, W. Xu, and P. Zavracky, Rothko: A Three Dimensional FPGA, IEEE Design and Test Magazine, Spring 1998, pp. 16-23.


Refereed conference papers

  1. C. Wu and W. Meleis, Optimized Kanerva-based Function Approximation for Multi-Agent Systems, Proceedings of the 7th International Conference on Autonomous Agents and Multiagent Systems (AAMAS), Estoril, Portugal, 2008.
  2. J. Zhang, W. Meleis, D. Kaeli and T. Wu, Acceleration of Maximum Likelihood Estimation for Tomosynthesis Mamography, The 12th International Conference on Parallel and Distributed Systems, pp. 291-299, Minneapolis, MN, 2006.
  3. M. Fayyazi, D. Kaeli and W. Meleis, A Polylogarithmic Time Parallel Maximum Weight Bipartite Matching Algorithm for Scheduling in Input-Queued Switches, Proceedings of International Parallel and Distributed Processing Symposium (IPDPS), Santa Fe NM, 2004.
  4. T. Wu, R. Moore, J. Zhang, E. Rafferty, D. Kopans, W. Meleis and D. Kaeli, Digital tomosynthesis mammography using a parallel maximum likelihood reconstruction method, Proceedings of SPIE: Medical Imaging, pp. 1-4, San Diego CA, 2004.
  5. H. Quinn, L. A. S. King, M. Leeser, and W. Meleis, Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines, IEEE Symposium on FPGAs for Custom Computing Machines, Napa CA, 2003, p. 173.
  6. F. Karimi, W. Meleis, Z. Navabi, and F. Lombardi, Data Compression for System-On-Chip Testing using ATE, 17th IEEE Intl. Symposium on Defect and Fault Tolerance in VLSI Systems, Vancouver, Canada, 2002, pp. 166-174.
  7. A. Eichenberger, W. Meleis, and S. Maradani, An Integrated Approach to Accelerate Data and Predicate Computations in Hyperblocks, 33rd Annual Intl. Conf. on Microarchitecture (IEEE/ACM), Monterey CA, Dec. 2000, pp. 101-111.
  8. S. Abraham, W. Meleis, and I. Baev, Efficient backtracking instruction schedulers, Intl. Conf. on Parallel Architectures and Compilation Techniques (IEEE/ACM), Philadelphia, PA, 2000, pp. 301-308.
  9. I. Baev, W. Meleis and A. Eichenberger, Lower Bounds on Precedence-constrained Scheduling for Parallel Processors, Intl. Conf. on Parallel Processing, Toronto, Canada, 2000, 549-553.
  10. A. Eichenberger and W. Meleis, Balance Scheduling: Weighing Branch Tradeoffs in Superblocks, 32nd Annual Intl. Conf. on Microarchitecture (IEEE/ACM), 1999, pp. 272.
  11. I. Baev, W. Meleis, and A. Eichenberger, Algorithms for Total Weighted Completion Time Scheduling, ACM-SIAM Symp. on Discrete Algorithms, January 1999.
  12. W. Meleis and E. Davidson, Optimal Dual-Issue Instruction Scheduling With Spills for Binary Expression Trees, ACM-SIAM Symp. on Discrete Algorithms, January 1999.
  13. J. Casmira, J. Fraser, D. Kaeli, and W. Meleis, Operating System Impact on Trace-Driven Simulation, 31st Annual Simulation Symp., April 1998.
  14. S. Sair, D. Kaeli, and W. Meleis, A Study of Loop Unrolling for VLIW-Based DSP Processors, IEEE Workshop on Signal Processing Systems, 1998, pp. 519 -527.
  15. M. Leeser, W. Meleis, M. Vai, and P. Zavracky, Rothko: a Three Dimensional FPGA Architecture, its Fabrication, and Design Tools, IEEE Conf. on Advanced Research in VLSI (ARVLSI), 1997.
  16. W. Meleis and E. Davidson, Optimal Local Register Allocation for a Multiple-Issue Machine, ACM Intl. Conf. on Supercomputing, pp 107-116, July 1994.


Other papers and presentations

  1. I. Baev and W. Meleis, Total Weighted Completion Time Scheduling for Superblocks, SIAM Conference on Discrete Mathematics, January 1998.
  2. J. Kalamatanos, A. Khalafi, D. Kaeli, and W. Meleis, Memory Performance Tuning Using Graph-based Analysis, Workshop on Pre-Hardware Performance Analysis Techniques, June 1998.
  3. K. Bowers, D. Kaeli, and W. Meleis, Performance Optimization of the Forth Interpreter, Northeastern University Technical Report ECE-CEG-98-022, 1998.
  4. W. Meleis, M. Leeser, P. Zavracky, and M. Vai, Architectural Design of a Three-Dimensional FPGA, Workshop on Field-Programmable Logic and Applications (FPL), 1997.


Students


Courses


Awards

Computer Engineering Group
Electrical and Computer Engineering Department
Northeastern University