RESUME OF FABRIZIO LOMBARDI - December 2, 2000

RESUME OF FABRIZIO LOMBARDI: December 2, 2000.

Chair and International Test Conference Endowed Professor,
Department of Electrical and Computer Engineering,
Northeastern University
309 Dana Research Building
Boston, Massachusetts 02115

Date and Place of birth: August 6, 1955 in Formia, Italy
Marital Status: Married, two children (a girl and a boy)
Citizenship: US

Education:

Ph.D., University College London, University of London, 1982. (Ph.D. Thesis Title: Modelling and Analysis of Fault Tolerant Microcomputer Systems ).
M.Sc. in Microwaves and Modern Optics, University College London, University of London, 1978.
Dipl. in Microwave Engineering, University College London, University of London, 1978.
B.Sc. in Electronic Engineering (Hons), University of Essex, 1977.

Specializations and Research Interests:

Fault-Tolerant Computing, VLSI CAD, Testing, Configurable Computing, Distributed Systems.

Record of Employment:

1998-present: Chairperson and Holder of the International Test Conference (ITC) Endowed Professorship, Department of Electrical and Computer Engineering, Northeastern University, Boston.
1993-1998, Full Professor and Holder of Halliburton Professorship (1995), Department of Computer Science, Texas A&M University, College Station.
1991-1998, Courtesy Appointment in the Department of Electrical Engineering, Texas A&M University, College Station.
1989-1994, Graduate Program Advisor, Department of Computer Science, Texas A&M University, College Station.
1988-1993, Associate Professor of Computer Science, Texas A&M University, College Station.
1984-1988, Assistant Professor of Electrical and Computer Engineering and Assistant Professor in the Telecommunication Graduate Program, University of Colorado at Boulder.
1982-1984, Assistant Professor of Computer Science/Electrical Engineering, Texas Tech University, Lubbock.
1978-1982, Research Assistant, Microwave Research Unit, University College London.
1978-1980, Research Associate, Cardiothoracic Institute, Department of Clinical Pharmacology, University of London Medical Postgraduate School, Brompton Hospital, London.

Awards:

Cardiothoracic Institute Research Support Award, United Kingdom (1978-1979).
National Research and Development Corporation Research Support Award, United Kingdom (1979-1980).
IEEE/Engineering Foundation's Research Award, USA (1985).
British Columbia Advanced Systems Institute/University of Victoria Visiting Fellow, Canada (1988-89).
Texas Engineering Experimental Station Research Fellow (1991-92 and 1997-1998).
Selected as Key Faculty Researcher "because of the nature and industry relevance of pursued research" from the Industrial/Federal Government Steering Committee on National Technology Policy to provide guidance on Transfer and Commercialization of University-Originated Technologies for major research Laboratories such as Sematech, Nasa and SRC (only 100 faculty researchers from US Universities have been selected) (1992).
Faculty Recognition Award, College of Engineering Texas A&M University and The Texas Engineering Experimental Station, (1993,1995).
Distinguished Visitor of the IEEE Computer Society, (1990-93).
International Research Program Award, Japan Advanced Institute of Science and Technology (JAIST), Japan (1993-1999).
Halliburton Professorship, Texas A&M University (1995).
Silver Quill Award, Motorola, Austin (1996).
Certificate of Appreciation, TC on Test Technology, IEEE Computer Society (1998).
Certificate of Appreciation, TC on Test Technology, IEEE Computer Society (1999).

Courses Taught:

Graduate Level (600 level): Fault Tolerant Computing (TTU,CU,TAMU), Microwave Techniques (UCL), Digital Computer Design (TTU), Digital Communication Systems (CU), Digital Network Systems (CU), Integrated System Design Automation (TAMU), Advanced Computer Systems Design (TAMU), Defect Tolerance (TAMU), Array Systems (TAMU), Testing and Diagnosis of Digital Systems (TAMU), Advanced Logic Design (TAMU), Computer Architecture (TAMU).
Upper Undergraduate Level (Senior only)(400 and 500 level): Analog and Digital Computation (TTU), Microprocessors (TTU), Electromagnetic Theory (TTU), Computer Organization (CU,TAMU), Switching and Finite Automata (CU).
Other Undergraduate Courses (300 level and lower): Logic Laboratory (TTU), Introduction to Programming (TTU), Microprocessors (TTU), Microcomputer Architecture and Programming (CU), Engineering Problem Solving and Computing (TAMU).

Graduate Students Supervision:

Major advisor only;

Master Degree with thesis:

S. Ratheal, "Reconfiguration Strategies in Multiprocessing Systems," TTU, April 1984.

A.M. Azmi, "A Floating Point System with Variable Length Exponent" CU, June 1987.

C.M. Kao, "Design of Testable Homogeneous VLSI Structures," TAMU, December 1989.

P.Y.M. Koo, "Yield Enhancement of VLSI/WSI Array Systems" TAMU, December 1989.

J. Salinas, "The F-Path Approach for Pattern Generation in Microprocessor Testing" TAMU, August 1991.

D. Ray, "A Novel Approach for Generating Multiple Unique Input/Output Sequences for Conformance Testing of Protocols" TAMU, December 1991.

C. Feng, "Detectability and Fault Detection Techniques for Finite State Machines," TAMU, May 1992.

U. Arunkumar, "Verification and Validation of Timed Protocols," TAMU, May 1992.

G. Menta, "A Hierarchical Approach to Conformance Testing of Protocols," TAMU, August 1992.

M. V. Bommena, "C-Testability of a Ripple-Carry Adder under Multiple Faults, TAMU, August, 1992, (with Dr. K. Watson, EE Department).

M. Sathyanarayana, "Generation of Test Sequences for Programmable Logic Array-Based Finite State Machines," TAMU, May 1994.

R. T. Wilkinson, "Performance Evaluation of Scalable Fault-Tolerant Parallel Computing Systems, TAMU, May 1996. (with Dr. D. Avresky, CS Department).

D. G. Ashen, "A Comprehensive Test Method for Reprogrammable FPGAs," TAMU, August 1996 (with Dr. D. Ross, EE Department).

L. Zhao, "Iddq Testing of FPGAs", TAMU, August 1997, (with Dr. D.H. Walker, CS Dept),

D. Krishnamoorthy, "Performance Evaluation of Configurable Arrays with Mesh Interconnections and Wormhole Routing," TAMU, December 1997.

B. Liu, "A New Approach to Test Programmable Wiring Networks for VLSI," TAMU, May 1998.

S.J. Ruiwale, "Testing Dynamically Reconfigurable FPGAs," TAMU, December 1998 (with Dr. G. Choi, EE Department).

E. Mizan, Northeastern University, in progress.

X. Liu, Northeastern University, in progress.

Master Degree with project:

Chanda, "Fault Detection in Fine-Grain Hierarchically-Connected FPGAs by Gate-Level Simulation," TAMU, August 1998.

External examiner for David Wessels (M. S. University of Victoria, Canada, 1990).

Ph.D. Degree

D. Sciuto (currently a Full Professor with the Politecnico di Milano, Italy), "Testing and Reconfiguration Techniques for VLSI Processor Arrays", CU, November 1988.

X. Sun (currently with Motorola, Semiconductor Products Sector, Austin), "Automatic Conformance Testing of Protocols Implemented in Software or Hardware," TAMU, August 1993.

Y.-N. Shen (currently with AMD-Vantis, San Jose), "Verification and Validation of Finite State Machines," TAMU, December 1993.

J. Salinas (currently with the Applied Research Laboratory, TAMU, College Station). "Reconfigurable and Testable Computer Systems for WSI," TAMU, August 1994.

S. S. Kim (currently an Assistant Professor with Ajou University, Seoul), "Modeling Fault Tolerance and Testing in Complex Digital Systems," TAMU, August 1995.

T. Liu (currently with Actel, San Jose), "Design and Test of Programmable Interconnects for Digital Systems," TAMU, August 1995.

C. Feng (currently with Ameritch, Chicago), "Adaptive Fault Diagnosis for Multicomputer Systems," TAMU, August 1995, (with L. Bhuyan).

H.H. Kari (currently with Nokia Telecomm., Helsinki), "Latent Sector Faults and Reliability of Disk Arrays," Helsinki Institute of Technology (Finland), June 1997.

N. Park (currently an Assistant Professor with Oklahoma State University), "Modeling and Evaluating the Quality Assurance of Multi-Chip Module Systems," TAMU, June 1997.

X.T. Chen (currently with Lucent Bell Labs, Allentown), "A Computer-Aided Testing Framework for Field Programmable Gate Arrays: from Verification to Configuration," TAMU, August 1997.

D. Schin (currently with Sprint Communication, Kansas City), "Algorithms and Techniques for Unique Input/Output Sequence Generation," TAMU, August 1998.

W. Feng (currently with Lucent Bell Labs, Allentown), "Computer-Aided Testing of Switching and Interconnect Resources of FPGAs," TAMU, December 1998.

J. Zhao (currently with Lucent Bell Labs, Allentown), "Interconnect Testing of Embedded Memories at Chip and System Level," TAMU, May 1999.

M. Al-Hashimi (currently an associate Professor with King Abdulaziz University, Jeddah, Saudi Arabia), "Fault Tolerance in Multiprocessor Systems by N-Modular Redundancy on Demand," TAMU, May 2000.

Y. An, (currently with Lucent Technologies, Naperville) "Reliable Strategies for Wireless Mobile Environments," TAMU, August 2000.

F. Karimi, Northeastern University, in progress.

X. Wang, Northeastern University, in progress.

A. Khalili, Northeastern University, in progress.

N. Natchev, Northeastern University, in progress.

Research Associates:

W.-K. Huang (Fudan University, PRC), 1986-1987, University of Colorado,

Y.-N. Shen (Fudan University, PRC), 1988-1991, University of Colorado and Texas A&M University.

T. Liu (Academy of Sciences, PRC), 1990-1991, Texas A&M University.

M.S. Kim (Korean Army Academy), 1992-1993, Texas A&M University.

P. Liu (Academia Sinica, PRC), 1992-1993, Texas A&M University.

Q. Chi (Xi'an Jiaotong University, PRC), 1993, Texas A&M University.

J. Tong (Fudan University, PRC), 1995-1996, Texas A&M University.

W.K. Huang (Fudan University, PRC), 1994-1996, Texas A&M University.

F.J. Meyer, 1996-1998, Texas A&M University.

Professional Societies:

Institute of Electrical and Electronics Engineers (IEEE), Computer Society (Member).
European Association of Microprocessing and Microprogramming (EAMM) (Member).
Association for Computing Machinery (ACM), SIGARCH, SIGMETRICS (Member).
Society for Industrial and Applied Mathematics (SIAM) (Member).
Eta Kappa Nu, Honorary Society of Electrical Engineers.
Who's Who in Frontiers of Science and Technology, 2nd Edition, November 1985.
Member of IEEE Computer Society Technical Committees on Distributed Processing, Fault-Tolerant Computing, Real-Time Systems, VLSI, Test Technology, Computer Architecture.
Member of IEEE Test Technology Technical Committee on Defect and Fault Tolerance.

Professional Service (Conferences and Symposia):

Participant to NASA/AIAA Workshop on Applied Fault Tolerant Computing for Aerospace Systems, Fort Worth, 1982.
President Undergraduate Research Award (with H.E. Harvey), Texas Tech University, 1982.
Session Chairman at 1983 IEEE Region 5 Conf. on Technology for an Efficient Tomorrow, "Special Problems," Houston, April 1983.
Session Chairman at 1983 Conference on Information Sciences and Systems, "Fault Analysis" The Johns Hopkins University, Baltimore, March 1983.
Invited Participant to NASA/IEEE Workshop on Laboratories for Reliable System Research, Langley, April 1983.
Organizer and Chairman of 2 Special Sessions on "Test Technology for Large Scale Systems: I, Theory; II, Practice," IEEE Int. Symp. on Circuits-and-Systems , Montreal, May 1984.
Organizer and Chairman of a Session on "Fault Tolerant Computing" IEEE Phoenix Conference on Computers and Communications, March 1985.
Co-Organizer and Chairman of a Panel Session on "Diagnostics and Fault Tolerance" 1st IEEE International Conference on Supercomputing Systems, St. Petersburg, December 1985 (with A.T. Dahbura).
Program Committee Member to IEEE Real-Time Systems Symposium, New Orleans, December 1986.
Session Chairman on "Design for Testability and Fault Tolerance" 12th Symposium on Microprocessing and Microprogramming, Venice, September 1986.
Session Chairman on "Multiprocessors: Short Notes," 12th Symposium on Microprocessing and Microprogramming, Venice, September 1986.
Co-Director, NATO Advanced Study Institute on Testing and Diagnosis of VLSI and ULSI, Como, July 1987.
Invited Participant to IFIP Workshop on Wafer Scale Integration, London, September 1987
Session Chairman on "Real-Time System Design," IEEE Real-Time Systems Symposium, San Jose, December 1987.
Program Committee Member, IEEE Real-Time Systems Symposium, Huntsville, December 1988.
Program Committee Member, IFIP Workshop on WSI, Como (Italy), June 1989; session chairman on "Architectures II".
Program Committee Member, Euromicro Workshop on Real-Time, Como (Italy), June 1989; session chairman on "Testing and Fault Tolerance".
Invited Keynote Speaker, 4th Technical Workshop: New Directions for IC Testing, Victoria (Canada), October 1989.
Program Committee Member, IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Hidden Valley, November 1991.
Session Chairman on "Fault Tolerance", IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Hidden Valley, November 1991.
Session Chairman on "Reconfigurable Array Concepts," IEEE Int. Conf. on WSI, San Francisco, January 1992.
Member of the panel on "Conformance Testing," 1992 Int. Phoenix Conf. on Computers and Comm., Phoenix, April 1992.
Program Committee Member, IEEE Fault Tolerant Computing Symposium, Boston, June 1992.
Session Chairman on "Synthesis for Testability and Fault Protection," IEEE Fault Tolerant Computing Symposium, Boston, June 1992.
Program Chairman, IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Dallas, November 1992.
Topic Coordinator "Recent Advances," IEEE VLSI Test Symposium, Atlantic City, April 1992.
Program Committee Member, Int. Workshop on Algorithms and Data Structures (WADS), Montreal, August 1993.
Session Chairman on "Numerical Algorithms," ICPP, St. Charles, August 1993.
Session Chairman on "Reconfiguration," IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Venice October 1993.
General Chairman, IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Venice, October 1993.
Session Chairman on "Testability," IEEE International Conference on WSI, San Francisco, January 1994.
Vice General Chairman, IEEE Int. Workshop on Fault Tolerance in Parallel and Distributed Systems, College Station, June 1994.
Program Committee Member, IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Montreal, October 1994; session chair on "Testable Architectures".
Program Committee Member, International Symposium on Parallel Architectures, Algorithms and Networks, Kanazawa, December 1994; session chair on "Fault Tolerance".
Program Committee Member, 1st IEEE Int. On-Line Testing Workshop, Nice, July 4-5, 1995.
Invited Guest Speaker, 6th Symposium on Fault Tolerant Computers (Simposio de Computadores Tolerantes a Falhas), Brazilan Computer Society (Sociedade Brasileira de Computacao), Canela, August 1995.
Program Committee Member, IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Lafayette, November 1995.
Publicity and Publication Chair, 2nd IEEE Int. Symp. on High Performance Comp. Arch., San Jose, January 1996.
Member of panel on "Can defect-tolerant chips better meet the quality challenge?" IEEE VLSI Test Symposium, Princeton, May, 1996.
Program Committee Member, Int. Symp. on Parallel Architectures, Algorithms and Networks, Beijing, June 1996.
General Chairman, IEEE Int. Workshop on Embedded Fault-Tolerant Systems, Dallas, September, 1996.
Program Committee Member, IEEE Int. Conference on Innovative Systems on Silicon, Austin, October 1996.
Session Chairman on "Testing and Yield," IEEE Int. Conference on Innovative Systems on Silicon, Austin, October 1996.
Program Committee Member, 4th Annual Workshop on Real-Time Applications, Montreal, October 1996.
Steering Committee Member, IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, Boston, November, 1996.
Program Committee Member, IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, Boston, November, 1996.
Member of panel on "On-Chip Testing," IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, November 1996.
Session Chairman on "Defect Avoidance," IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, November 1996.
General Chair, IEEE Int. Workshop on Memory Technology, Design and Testing, San Jose, August 1997.
Program Committee Member and Topic Chair "Reconfiguration, Defect and Fault Tolerance," IEEE Int. Conf. On Innovative Systems on Silicon, Austin, October 1997.
Session Chairman on "Innovations in Testing," IEEE Int. Conf. On Innovative Systems on silicon, Austin, October 1997.
Program Committee Member, IEEE Int. Conf. on Defect and Fault Tolerance in VLSI Systems, Paris, November 1997.
Session Chairman on "Self-Checking and Coding," IEEE Int. Conf. on Defect and Fault Tolerance in VLSI Systems, Paris, November, 1997.
Program Committee Member, IEEE/ACM Int. Conf. on FPGAs, Monterey, February 1998.
Session Chairman on "Technology Mapping for FPGAs," ACM Int. Symp. on FPGAs, Monterey, February 1998.
Program Committee Member, IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, Orlando, April 1998.
Program Chair, IEEE Int. Workshop on Embedded Fault-Tolerant Systems, Boston, May 1998.
Session Chairman on "Hardware/Software Co-Design of Embedded Computing Systems," IEEE Int. Workshop on Embedded Fault-Tolerant Systems, Boston, May 1998.
Program Committee Member, IEEE Int. Conference on Parallel Processing, August 1998.
General Chair, IEEE Int. Workshop on Memory Technology, Design and Testing, San Jose, August 1998.
Program Committee Member, 7th IEEE Int. Conf. on Computer Communications amd Networks, Lafayette, October 1998.
Program Committee Member, PACT'98 Workshop on Reconfigurable Computing, Paris, October 1998.
Program Committee Member, IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, Austin, October, 1998.
Program Committee Member, IEEE/ACM Int. Conf. on FPGAs, Monterey, February 1999.
Program Committee Member, RAW'99: the 6th Reconfigurable Architectures Workshop, San Juan de Puerto Rico, April 1999.
Program Committee Member, 8th IEEE North Atlantic Test Workshop, West Greenwich, May 1999.
Session Chiarman on "Verification and Functional Test," 8th IEEE North Atlantic Test Workshop, West Greenwich, May 1999.
Program Committee Member, IEEE International Symposium on Memory Technology, Design and Testing, San Jose, August 1999.
Session Chairman on "Architecture and Applications," IEEE Symposium on Memory Technology, Design and Testing, San Jose, August 1999.
Program Committee Member, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Alberqueque, October 1999.
Program Committee Member, IEEE/ACM International Conference on FPGAs, Monterey, February 2000.
Program Committee Member, RAW'2000: the 7th Reconfigurable Architectures Workshop, Cancun, May 2000.
Program Committee Member, 9th IEEE North Atlantic Test Workshop, Gloucester, May 2000.
Program Committee Member, IEEE International Workshop on Solving the Memory Wall, Vancouver, June 2000.
Session Chairman on "Memory Technology", IEEE International Workshop on Solving the Memory Wall, Vancouver, June 2000.
Program Committee Member, IEEE International Symposium on Memory Technology, Design and Testing, San Jose, August 2000.
Session Chairman on "New Ideas," IEEE International Symposium on Memory Technology, Design and Testing, San Jose, August 2000.
General Co-Chair, IEEE International Workshop on Embedded Fault-Tolerant Systems, Washington, September 2000.
Program Committee Member, IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Mt. Fuji-Yamanashi, October 2000.
Session Chairman on "BIST," IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Mt. Fuji-Yamanashi, October 2000.
Program Committee Member, 10th IEEE North Atlantic Test Workshop, Gloucester, May 2001.

Professional Service (Editorial and Refereeing):

Associate Editor, IEEE Transactions on Computers, 1996-present.
Associate Editor, IEEE Design and Test, 1999-present.
Member Advisory Editorial Board, Journal of Microelectronic System Integration, Plenum Press, 1993- present.
Editorial Correspondent in the USA for Euromicro, 1986 - 88.
Invited Guest Editor of a Special Issue on Fault Tolerant Computing, Microprocessing and Microprogramming, North Holland Publ. Co., vol. 20, no. 4-5, June 1987.
Invited Guest Editor of a Special Issue on Defect and Fault Tolerance in VLSI Systems, Journal of Microelectronic System Integration, vol. 3, No. 2, Plenum Press, June 1995.
Invited Guest Editor of a Special Issue on "Field Programmable Gate Arrays," IEEE Design & Test Magazine, vol. 15, No. 1, 1998.
Invited Guest Editor (with D. R. Avresky, K.E. Grosspiesch, and B. W. Johnson) of a Special Issue on "Embedded Fault-Tolerant Systems," IEEE Micro Magazine , vol. 18, no. 5, 1998.
Invited Guest Editor (with B. Cockburn and F.J. Meyer) of a Special Issue on "DRAM Architecture and Testing," IEEE Design and Test Magazine, vol. 16, no. 1, 1999.
Invited Guest Editor (with J.L. Gaudiot) of a Special Issue on "Configurable Computing," IEEE Transactions on Computers, vol. 48, no. 6, pp. 553-555, 1999.
Invited Guest Editor (with D. Avresky and B.J. Johnson), of a Special Issue on "Embedded Fault-Tolerant Systems," Journal of Supercomputing: High Performance Computer Design. Analysis and Use, Vol. 16, No. 1/2, Kluwer Academic Press, May 2000.
Invited Guest Editor (with M.G. Sami) of a Special Issue on "Defect Tolerance in Digital Systems," IEEE Transaction on Computers, Vol. 49, No. 6, June 2000.
Invited Guest Editor (with C. Metra), of a Special Issue on "Defect-Oriented Diagnosis for Very Deep Submicron Systems," IEEE Design and Test Magazine, Spring 2001.
Invited Guest Editor (with D. Avresky and B.W. Johnson) of a Special Issue on "Fault Tolerant Embedded Computer Systems," IEEE Transactions on Computers. June 2001.
Invited Guest Editor (with D. Kaeli and H. Hadimioglu) of a Special Issue on "Advances in High Performance Memory Systems," IEEE Transactions on Computers, November 2001.
Member Editorial Board, IEEE Press Book Series: Microelectronic Systems Principles and Practice, 1997-current.
Referee of IEEE Computer Magazine, 1990-1996.
Referee of IEEE International Test Conference, 1982-present.
Referee of IEEE Transactions on Communications, 1991-1996.
Referee of IEE Transactions on Software and Microsystems, 1982-1986.
Referee of ISA (Instrumentation Society of America), 1983.
Referee of IEEE Fault Tolerant Computing Symposium, 1983-present.
Referee of IEEE VLSI Test Symposium, 1992-present.
Referee of IEEE Transactions on Computers, 1984-present.
Referee of IEEE Transactions on CAD, 1988-present.
Referee of Int. Conference on Parallel Processing, 1984-1987, 1993-1997.
Referee of IEE Proc. on Computers and Digital Techniques, 1984-1993.
Referee of IEEE Transactions on Parallel and Distributed Computing, 1990-1998.
Referee of IEEE Transactions on VLSI Systems, 1992-present.
Referee of JETTA, 1991-1998.
Referee of IEEE Transactions on CPMT, 1994-1998.
Referee IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1996-present.
Panelist, NSF Proposal Review Panel for the Design Automation Program (Testing), February 1999.
Panelist, NSF Proposal Review Panel for the Computer Systems Architecture Program (Embedded/reconfigurable Architecture), February 1999.
Referee of NSERC, Canada, 1990-present.
Referee of NSF, 1989-present.

Funded Research:

Availability Analysis and Modelling of Parallel Processing Architectures, ONR Contract No. 76-C-1136, $19,250 (Unit 6, Joint Services Electronics Program), 1983-1984 ( Co-PI, Principal Investigator: R. Saeks).

Analysis and Design of Large Scale Computing Systems, ONR Contract No. 14-84-C-0104, $19,630, 1984-1985 (Co-PI, Principal Investigator: R. Hunt).

PI, Diagnosable Systems for Fault Tolerant Computing, IEEE/Engineering Foundation, $17,000, 1985-1986.

PI, A Laboratory for VLSI Testing and Diagnosis, AT&T IS Division, $25,000, 1985.

PI, Analysis and Evaluation of Class of Synchronous Architecture for Parallel Processing and Fault Tolerant Computing, AT&T Foundation, $69,200, 1985-1987.

PI, Fault Tolerance and Diagnosis in VLSI Systems, NATO Collaborative Research Grant, $10,166 , 1986-1988 (with M.G. Sami).

PI, Testing and Diagnosis of VLSI and ULSI, NATO-ASI, $35,000, 1986-1987 (with M.G. Sami).

PI, A Comprehensive Research Program on Large Scale Systems for Advanced Computing, AT&T Foundation, $40,000, 1986-87.

PI, Computer Aided Testing and Design for VLSI and WSI, AT&T Information Systems, $40,000, 1987-88.

PI, VLSI Testing, Texas A&M University Engineering Excellence Fund, $26,000, 1988-89.

PI, Wafer Scale Integration, IFIP Travel Grant, $750, 1989.

PI, Defect and Fault Tolerance in VLSI Systems, NSF Travel Grant, $1,200, 1990.

PI, Graduate Research Fellowship (for H.H. Kari), Foundation of Jenny and Antti Wihuri, Helsinki (Finland), $20,000, 1991.

PI, Graduate Research Fellowship (for H.H. Kari), Finnish Cultural Fund, Helsinki (Finland), $20,000, 1992.

PI, Testable Approaches and Design for Array Systems, NSF, MIPS Division, $80,000, 1991-93.

Studies on Self-Reconfigurable Massively Parallel Computers, Japan Ministry of Education, Science and Culture, $282,600, (Grant Number 05044090), 1993-96 (Co-PI, Principal Investigator: S. Horiguchi).

Fault Tolerance in Multiprocessor Arrays, Texas Advanced Technology Program - Research (Computer and Information Engineering), $260,000 (inclusive of $80,000 matching funds from Texas A&M University) 1994-96 (Co-PI, Principal Investigator: L. Bhuyan).

PI, "Testable and Fault Tolerant Design of Programmable Chips by Technology Mapping," Texas Advanced Research Program (Engineering), $232,551 (inclusive of $68,910 matching funds from Texas A&M University), 1996-1998.

"New Interconnection Schemes for Massively Parallel and Distributed Systems," Japan Ministry of Education, Science and Culture, $65,000, 1997-1999, (Co-PI, PI: Susumu Horiguchi).

PI, "Computer Engineering Capstone Design," Lockheed-Sanders, $10,000, 1999-2000.

PI, "Research in System-on-Chip Testing," LTX Corporation, $145,000, 1999-2000 (with F.J. Meyer).

PI, "Research in IC Manufacturing," Lucent Technologies Allentown, $75,000, 1999-2000.

PI, "Research in DSP and Computer Networks," Lucent Technologies Andover, $716,000, 2000-2001.

Invited Seminars:

1981: Northwestern University, University of London.
1983: University of Massachusetts - Amherst, Rice University, Arizona State University, Polytechnic Institute of New York, University of Colorado-Boulder, Virginia Polytechnic Institute and State University.
1984: University College London, University of Roma.
1985: University of Maryland-College Park, AT&T Information Systems - Broomfield.
1986: Politecnico di Milano, AT&T ISL-Denver.
1987: University of New Mexico, AT&T Bell Laboratories-Murray Hill, University of Victoria, Arizona State University, AT&T Information Systems-Denver.
1988: Fudan University, Academia Sinica-Beijing, University of Victoria.
1989: University of Victoria, University of British Columbia, Simon Frazier University.
1990: IBM-SID Houston, University of Victoria.
1991: University of Manchester Institute of Science and Technology, E-Systems-Greenville.
1992: University of Texas-Arlington, IEEE Circuits and Systems Society (Dallas Section).
1993: Texas Tech University, Colorado State University, IEEE Computer Society (Denver Section).
1994: Toyo University, Japan Advanced Institute of Science and Technology, University of Essex, ITRI-Austin.
1995: University of Sao Paulo at Sao Carlos.
1996: University of Houston, NTT Musashino Research and Development Center, Japan Advanced Institute of Science and Technology.
1997: Keio University, Japan Advanced Institute of Science and Technology.
1998: Northeastern University, University of Alberta, University of Connecticut, University of Oklahoma, University of Alabama-Huntsville, Yale University.
1999: Japan Advanced Institute of Science and Technology.
2000: Oklahoma State University.

Academic Consultancy:

IBM, University Program on "Reliability, Availability and Serviceability", Austin, 1983-1984.

International Communication Association, Professional Development Course on "Controlling Transmission Errors", Boulder, June 1986.

Politecnico di Milano, Technical Consultant for the ESPRIT Microelectronics Program of the European Economic Community, 1986-87.

SGS Microelectronics, Technical Consultant on Iterative Logic Array Testing, February 1988.

MIT Press, Times Mirror Books, 1989.

State of Louisiana, Board of Regents, 1989-1990.

University of Texas-Austin, Continuing Eng. Education Program, professional course on Object Oriented Programming for IBM-Austin, 1990.

Ministry of Education and Science of Japan, Technical Consultant on Reconfigurable Massively Parallel Computers, 1993-1996.

Government of Brazil (Brazilian Computer Society and State of Sao Paulo), 1995.

Mc Graw-Hill Publ. Co, 1996.

Advanced Micro Devices-Vantis, PLD Division, Sunnyvale, 1997.

Ministry of Education and Science of Japan, Technical Consultant on Interconnection Schemes, 1997-1999.

Franklin, Beedle and Associates Publ Inc, 1998.

McGraw-Hill Publ. Company, 1998.

Member of the External Advisory Board, Department of Electrical and Computer Engineering, Stevens Institute of Technology, Hoboken, 2000- current.

Extensive consultancy activities on technology assessment and evaluation with financial/banking institutions.

BOOKS.

"Testing and Diagnosis of VLSI and ULSI," F. Lombardi and M.G. Sami (Eds), 533 pages, Series E: Applied Science, vol. 151, NATO ASI Series, Kluwer Academic Publishers, Dordrecht/Boston/London, 1988, (ISBN 90-247-3794-X). The following chapters were written and appear in the above book:

"Reconfiguration of Orthogonal Arrays by Front Deletion", pp.429-468, (with C-L Wey).

"Old and New Approaches for the Repair of Redundant Memories," pp. 383-428.

"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems," Proceedings, D.H. Walker and F. Lombardi (Eds), 335 pages, IEEE Computer Society Press, Washington, 1992, (ISBN 0-8186-2837-5).

"IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems," Proceedings, F. Lombardi, M. G. Sami, Y. Savaria and R. Stefanelli (Eds), 336 pages, IEEE Computer Society Press, Washington, 1993, (ISBN 0-8186-3502-9).

"IEEE International Workshop on Memory Technology, Design and Testing," Proceedings, F. Lombardi, R. Rajsuman and T Wik (Eds), 103 pages, IEEE Computer Society Press, Washington, 1997, (ISBN 0-8186-8099-7).

"Verification and Validation of Protocols Using Multiple Unique Input/Output Sequences," by X. Sun, C. Feng, Y. N. Shen and F. Lombardi, Advanced Series in Electrical and Computer Engineering, World Scientific Publ., 272 pages, Vol. 12, 1997, (ISBN 981-02-2832-5).

"IEEE International Workshop on Memory Technology, Design and Testing," Proceedings, D. Lepejan, F. Lombardi, R. Rajsuman and T. Wik (Eds), 131 pages, IEEE Computer Society Press, Washington, 1998, (ISBN 0-8186-8494-1).

BOOK CHAPTERS

"VLSI Systems, Defect Tolerance," Encyclopedia of Microcomputers, Edited by A. Kent and J. G. Williams, vol. 20, pp, 143-157, Marcel Dekker Inc., New York, 1997 (with J. Pineda).

"Defect Tolerance in VLSI Systems," Encyclopedia of Computer Science and Technology, Edited by A. Kent and J.G. Williams, vol. 32, pp. 67-82, Marcel Dekker Inc. , New York, 1995 (with J. Pineda).

"Protocol Conformance Testing by Discriminating UIO Sequences," Protocol Specification, Testing, and Verification, XI, Edited by B. Jonsson, B. Pehrson and J. Parrow, pp. 349-364, Elsevier Science Publ. Co., Amsterdam, 1992 (with D. Sciuto, X. Sun and Y.-N. Shen).

"On Repairability/Unrepairability Detection and Yield Enhancement of WSI Redundant Memories," in Wafer Scale Integration: III, Edited by M.G. Sami and F. Distante, pp. 221-236, North Holland Publ. Co, The Nederlands, 1990 (with Y.-N. Shen).

"On Testable Redundant PLAs for WSI Implementation and Manufacturing," in Wafer Scale Integration: III, edited by M.G. Sami and F. Distante, pp.121-136, North Holland Publ. Co., The Nederlands, 1990 (with Y.-N. Shen).

"Protocol Conformance Testing Using Multiple UIO Sequences," in Protocol Specification, Testing and Verification, IX, Edited by E. Brinksma, G. Scollo and C.A. Vissers, pp. 131-143, Elsevier Science Publ. Co., Amsterdam, 1990 (with Y.-N. Shen and A.T. Dahbura).

"Orthogonal Mapping: A Reconfiguration Strategy for Fault Tolerant Two-Dimensional VLSI/WSI Arrays," in Defect and Fault Tolerance in VLSI Systems: I, Edited by I. Koren, pp. 309-318, Plenum Press, New York, 1989 (with L. Jervis and D. Sciuto).

"Design and Analysis of C-Testable Arrays," in Wafer Scale Integration Vol. II, Edited by R.M. Lea, pp. 115-123, North Holland Publishing Company, Amsterdam, 1988, (with W-K Huang and D. Sciuto).

"Algorithms for Delay-Bound Reconfiguration of Arrays," in Wafer Scale Integration, edited by G. Saucier and J. Trilhe, pp. 197-206, North Holland Publishing Company, Amsterdam, 1986 (with D. Sciuto).

"Availability Analysis of Fault Tolerant Microcomputer Systems with Periodic Preventive Replacement," in ``Microsystems: Architecture Integration and Use'' , C.J. Van Spronsen and L. Richter (eds.), pp. 185-191, North Holland Publ. Co., 1982 (with O.J. Davies).

LIST OF PUBLICATIONS - REFEREED JOURNALS

"Testing and Testable Designs for One-Time Programmable FPGAs," IEEE Transaction on CAD of ICAS , (with T. Liu, W.K. Huang and F. J. Meyer) (accepted).

"Analysis of Stratified Testing for Multi-chip Module Systems," IEEE Transactions on Reliability, (with N. Park) (accepted).

"Analysis and Diagnosis of Interconnect Faults in Bus Structured Systems," IEEE Design and Test, (with J. Zhao and F.J. Meyer) (accepted).

"Testing SRAM-Based Content Addressable Memories," IEEE Transactions on Computers, vol. 49, no. 10. pp. 1054-1063, 2000 (with J. Zhao, S. Irrinki and M. Puri).

"An Approach for Detecting Multiple Faulty FPGA Logic Blocks," IEEE Transactions on Computers, vol. 49, no. 1, pp. 48-54, 2000 (with W.K. Huang and F.J. Meyer).

"Adaptive Fault Detection and Diagnosis of Random Access Memories Interconnects," Journal of Electronic Testing: Theory and Applications (JETTA). Kluwer Academic Publishers, Boston vol. 15, no. 1/2, pp. 157-171, 1999 (with F.J. Meyer and J. Zhao).

"Reconfiguring One-Time Programmable FPGAs," IEEE Micro, vol. 19, no. 6, pp. 53-63, 1999 (with X. T. Chen, F.J. Meyer, W. Feng and J. Zhao).

"Fault-Tolerant Rank Order Filtering for Image Enhancement," IEEE Transactions on Consumer Electronics, vol. 45, no. 2, pp. 436-442, 1999 (with S.S. Kim and J.H. Kim).

"Design Verification of FPGA Implementations by Equivalent Classes," IEEE Design and Test, vol. 16, no. 2. pp. 66-73, 1999 (with X.T. Chen, W.K. Huang, N. Park and F.J. Meyer).

"Test Generation And Scheduling For Layout-Based Detection Of Bridge Faults In Interconnects," IEEE Trans. on VLSI Systems, vol. 7, no. 1, pp. 48-55, 1999 (with T. Liu, X. T. Chen and F.J. Meyer).

"Iddq Testing of Bridging Faults in Reconfigurable FPGAs," IEEE Transactions on Computers, vol. C47, no. 10, pp. 1136-1152, 1998 (with L. Zhao and D.M.H. Walker).

"Structural Diagnosis of Interconnects by Coloring," ACM Trans. on Design Automation of Electronic Systems, vol. 3, no. 2, pp. 249-271, 1998 (with X.T. Chen and F.J. Meyer).

"Testing Configurable LUT-based FPGAs," IEEE Trans. on VLSI Systems, vol 6, no. 2, pp. 276-283, 1998 (with W.K. Huang, X.T. Chen and F.J. Meyer).

"Testing of Programmable Logic Devices (PLD) with Faulty Resources," Int. Journal on Microelectronic Systems Integration, Special Issue on Defect and Fault Tolerance in VLSI Systems, vol. 5, no. 4, pp. 219-232, 1998, Plenum Press, (with D.G. Ashen, F.J. Meyer and N. Park).

"Structural Testing of Programmable Interconnects," Journal of Microelectronic Systems, vol 5, no. 3, pp. 129-144, 1997 Plenum Press, (with W. Feng and W.K. Huang).

"Modeling Testing Strategies for Yield Enhancement of MultiChip Module Systems," IEEE Trans. on Reliability, vol TR46, no. 2, pp. 184-192, 1997 (with S.S. Kim and N. Park).

"Analysis of Repair Algorithms for Mirrored-Disk Systems," IEEE Trans. on Reliability, vol. TR46, no. 2, pp. 193-200, 1997, (with H.H. Kari, H. Saikkonen, and N. Park).

"Graph Algorithms for Conformance Testing Using the Rural Chinese Postman Tour," SIAM Journal on Discrete Mathematics, vol. 9, no. 4, pp. 511-528, 1996 (with Y.-N. Shen).

"Adaptive System-Level Diagnosis for Hypercube Multiprocessors," IEEE Trans. on Computers, vol. C45, no. 10, pp. 1157-1170, 1996 (with L. Bhuyan and C. Feng).

"FsmTest: Functional Test Generation for Sequential Circuits," INTEGRATION: the VLSI Journal, vol. 20, no. 3, pp. 303-325, 1996 (with G. Buonanno, F. Fummi and D. Sciuto).

"On the Multiple Bridge Fault Diagnosis of Baseline Multistage Interconnection Networks," Trans. on Information and Systems of the Inst. of Elect. and Comp. Eng. of Japan, vol. E79D, no. 8, pp. 1151-1162, 1996 (with S. Horiguchi and N. Park).

"A Sweeping Line Approach to Interconnect Testing," IEEE Trans. on Computers, vol. C45, no. 8, pp. 917-929, 1996 (with Y.N. Shen and J. Salinas).

"Fault Tolerance in a VLSI Processor by Scheduling with Time Redundancy," Journal of Microelectronic Systems Integration, vol. 3, no. 4, pp. 219-234, Plenum Press, N.Y., 1996 (with S.S. Kim).

"A Structured Walking-1 Approach for the Diagnosis of Interconnects and FPICs," Trans. on Information and Systems of the Inst. of Elect. and Comp. Eng. of Japan, vol. E-79D, no. 1, pp. 29-40, 1996 (with T. Liu, S. Horiguchi and J.H. Kim).

"Diagnosis of Interconnects Using a Structured Walking-1 Approach," INTEGRATION: the VLSI Journal, vol. 19, no. 4, pp. 181-198, 1995 (with T. Liu).

"A Non-Memoryless Simulation Approach for the Evaluation of Computer Networks," Systems Analysis, Modelling and Simulation, vol. 20, pp. 255-276, 1995 (with H.H. Kari).

"Modeling Intermediate Tests for Fault Tolerant Multichip Module Systems," IEEE Trans. on Components, Packaging and Manufacturing Technology; Part B:Advanced Packaging, Special Issue on WSI, vol. 18, no. 3, pp. 448-455, 1995 (with S. S. Kim).

"An Optimal Reconfiguration Approach for Multipipeline Arrays," Journal of Microelectronic Systems Integration, vol. 1, no. 3/4, pp. 247-258, Plenum Press, N. Y., 1994 (with J. Salinas and C. Feng).

"On the Design for Testability of Sequential Circuits," IEE Computers and Digital Techniques, vol. 141, no. 3, pp. 153-160, 1994, (with X. Sun).

"On Generating Complex Non-Standard Random Distributions for Discrete Event Simulation Systems," Simulation: Practice and Theory, vol. 1, no. 1, pp. 173-193, Elsevier Science Publ. Co., Amsterdam, 1994, (with H. H. Kari and J. Salinas).

"On GID-Testable Two-Dimensional Iterative Arrys," Journal of Comput. Science and Technology, vol. 9, no. 1, pp. 27-36, 1994 (with W.K. Huang).

"Detecting Latent Sector Faults in SCSI Disks," ICL Technical Journal, vol.8, no. 4, pp. 655-663, 1993 (with H. H. Kari and H. Saikkonen).

"Fault Detection in TFCMOS/DFCMOS Combinational Gates," INTEGRATION: the VLSI Journal, vol. 15, no. 2, pp. 201-227, 1993 (with G. Buonanno, D. Sciuto and Y.-N. Shen).

"On the Testability of Array Structures for FFT Computation," Journal of Electronic Testing : Theory and Application (JETTA), vol. 4, no. 3, pp. 215-224, Kluwer Academic Publishers, Boston 1993 (with C. Feng and J. Muzio).

"Self-Testing Approaches for VLSI Arrays," IEE Computers and Digital Techniques, vol.140, no. 3, pp. 175-183, 1993 (with W.K. Huang).

"On the Optimal Reconfiguration of Multipipeline Arrays in the Presence of Faulty Processing and Switching Elements," IEEE Transactions on VLSI Systems, vol. 1, no. 1, pp. 76-79, 1993 (with H. Lin and M. Lu).

"On a Data Path Approach for Testing Microprocessors with a Fault Bound: the MC68000 Case," Microprocessors and Microsystems, Butterworth Scientific Publ. Co., London vol. 16, no. 10, pp. 529-539, 1992, (with J. Salinas).

"Detection and Location of Multiple Faults in Baseline Interconnection Networks," IEEE Trans. on Computers, vol. C41, no. 10, pp. 1340-1344, 1992 (with C. Feng and W.-K. Huang).

"Evaluation and Improvement of Fault Coverage of Conformance Testing by UIO Sequences," IEEE Transactions on Communications, vol. COM40, no. 8, pp. 1288-1293, 1992 (with Y.-N. Shen).

"Protocol Conformance Testing Using Multiple UIO Sequences," IEEE Trans. on Communications, vol. COM40, no. 8, pp. 1282-1287, 1992 (with Y.-N. Shen and A.T. Dahbura).

"Constant Testability of Combinational Cellular Tree Structures," Journal of Electronic Testing: Theory and Application (JETTA), vol. 3, no. 3, pp. 139-148, Kluwer Academic Publishers, Boston, 1992 (with D. Sciuto).

"On the Reduction of Programming Cost of Soft Switches for Reconfigurable Two-Dimensional Arrays," IEE Computers and Digital Techniques, vol. 139, no. 3, pp. 262-268, 1992 (with T. Liu).

"Concurrent Error Detection and Fault Location in A FFT Architecture," IEEE Journal of Solid-State Circuits, 4th Special Issue on Microelectronic Systems, vol. SC27, no. 5, pp. 728-736, 1992 (with J. Muzio).

"An FFT Architecture for WSI with Concurrent Error Detection and Fault Location," IEE Computers and Digital Techniques, vol. 139, no. 1, pp. 13-20, 1992 (with J. Muzio and Y.-N. Shen).

"Design for Testability Techniques for CMOS Combinational Gates," IEEE Trans. on Instr. and Measurements, vol. 40, no. 4, pp. 703-708, 1991 (with D. Sciuto, G. Buonanno and Y.- N. Shen).

"Minimizing the Cost of Repairing WSI Memories," INTEGRATION: the VLSI Journal, vol. 11, no. 4, pp. 279-293, North Holland Publ. Co, Amsterdam, 1991 (with W-K Huang).

"An Approach for the Reconfiguration of Multipipeline Arrays," IEE Computers and Digital Techniques, vol. 138, Pt. E, no. 3, pp. 131-137, 1991 (with P. Koo and Y.-N. Shen).

"A Fault Tolerant Tree Architecture with Improved Reconfiguration Capabilities," International Journal of Electronics, vol. 69, no. 6, pp. 723-746, 1990 (with Y.-N. Shen).

"On the Constant Diagnosability of Baseline Interconnection Networks," IEEE Trans. on Computers, vol. C39, no. 12, pp. 1485-1488, 1990 (with W-K Huang).

"Fault Detection and Design Complexity in C-Testable VLSI Arrays," IEEE Trans. on Computers, vol. C39, no. 12, pp. 1477-1481, 1990 (with W-K Huang).

"A Testable PLA for Manufacturing and Production," Journal of Semicustom ICs, vol. 8, no. 1, pp. 30-39, North Holland Publ. Co, Amsterdam, 1990, (with Y.-N. Shen).

"C-Testability of Two-Dimensional Sequential Arrays" Int. Journal of Electronics, vol. 69, no. 5, pp. 681-689, 1990, (with W-K Huang).

"A Repairability/Unrepairability Detection Technique for Yield Enhancement of VLSI/WSI Memories with Redundancy," IEE Computers and Digital Techniques, vol. 137, Pt. E, no. 2, pp. 133-136, 1990 (with Y.-N. Shen).

"Repairing VLSI/WSI Redundant Memories with Minimum Cost," Journal of Comput. Sci. and Tech., vol. 5, no. 2, pp. 187-196, 1990 (with W. -K. Huang).

"Yield Enhancement and Manufacturing Throughput of Redundant Memories by Repairability/Unrepairability Detection," Journal of Electronic Testing: Theory and Applications (JETTA), vol. 1, no. 1, pp. 43-57, Kluwer Academic Publishers, Boston 1990 (with Y.-N. Shen).

"New Approaches for the Repair of Memories by Row/Column Deletion for Yield Enhancement," IEEE Trans. on CAD of ICAS, vol. CAD9, no. 3, pp. 323-328, 1990 (with W-K Huang and Y.-N. Shen).

"On a New Class of C-Testable Systolic Arrays," INTEGRATION: the VLSI Journal, vol. 8, pp. 269-283, North Holland Publ. Co, Amsterdam, 1989.

"Reconfiguration of VLSI Arrays by Covering," IEEE Trans. on CAD of ICAS, vol. CAD8, no. 9, pp. 952-965, 1989 (with M.G. Sami and R. Stefanelli).

"Functional Testing and Verification of Array Systems," Microprocessors and Microsystems, vol. 13, no. 6, pp. 403-412, Butterworth Scientific Publ. Co., London, 1989, (with D. Sciuto).

"An Algorithm For Functional Reconfiguration of Fixed-Size Arrays" IEEE Trans on CAD of ICAS, vol. CAD7, no. 10, pp. 1114-1118, 1988 (with R. Stefanelli and D. Sciuto).

"Reconfiguration of Hexagonal Arrays by Diagonal Deletion, " INTEGRATION: the VLSI Journal, vol. 6, pp. 263-290, North Holland Publ. Co, Amsterdam, 1988.

"On an Improved Design Approach for C-Testable Orthogonal Iterative Arrays," IEEE Trans. on CAD of ICAS, vol. CAD7, no. 5, pp. 609-615, 1988 (with W-K Huang).

"On Functional Testing of Array Processors", IEEE Trans. on Computers vol. C37, no. 11, pp. 1480-1484, 1988 (with D. Sciuto).

"A Low Complexity Approach for Fault Detection in C-Testable Orthogonal VLSI Arrays," Microprocessing and Microprogramming, vol. 22, pp. 277-299, North Holland Publ. Co., Amsterdam, 1988 (with W-K Huang).

"A Fault Counting Algorithm for Repairing Redundant Memories," Int. Journal of Electronics, vol. 64, no. 6., pp. 869-884, 1988.

"A C-Testability Approach for Two Dimensional Iterative Arrays," Int. Journal of Electronics, vol. 64, no. 2, pp. 179-197, 1988 (with W-K. Huang).

"Analysis of Comparison-Based Diagnosable Systems using Temporal Criteria", The Computer Journal, vol. 31, no.3, pp. 201-208, The British Computer Society, Cambridge University Press, 1988.

"Algorithms for Functional Testing of Digital Systems," Int. Journal of Electronics, vol. 62, no. 5, pp. 707-732, 1987 (with C-L Wey).

"On the Repair of Redundant RAMs", IEEE Trans. on CAD of ICAS, vol. CAD6, no. 2, pp. 222-231, 1987 (with C-L Wey).

"On a Software Testbed for the Design and Evaluation of Distributed Computer Systems," Microprocessing and Microprogramming, vol. 19, no. 1, pp. 49-58, North Holland Publ. Co., Amsterdam, 1987 (with S. Ratheal).

"An Architecture and an Interconnection Scheme for Time-Sliced Buses," Journal of Parallel and Distributed Computing, vol. 4, no. 2, pp. 209-229, Academic Press, 1987 (with A. Kovaleski and S. Ratheal).

"On a Novel Self-Test Approach to Digital Testing," The Computer Journal, vol. 30, no. 3, pp. 258-267, The British Computer Society, Cambridge University Press 1987 (with C-L Wey).

"On the Design of a Redundant Programmable Logic Array (RPLA)," IEEE Journal of Solid-State Circuits, vol. SC22, no. 1, pp. 114-117, 1987 (with C-L Wey and M.K. Vai).

"On Comparison-based Diagnosis with Faulty Comparators," Electronics Letters, vol. 22, no. 22, pp. 1158-1160, IEE, London , 1986.

"Diagnosis by Comparison with Faulty Comparators," Microprocessing and Microprogramming, vol. 18, pp. 271-274, North Holland Publishing Co., Amsterdam 1986.

"Algorithms for Fault Identification in a Diagnosable Multi-Processor System" Electronics Letters, vol. 21, no. 9, pp. 405-406, IEE, London, 1985.

"Detection in Fault Tolerant Systems for Large Scale Computation," Electronics Letters, vol. 21, no. 2, pp. 50-52, IEE, London, 1985.

"Fault Diagnosis for a Multistage SW Banyan Interconnection Network", IEE Computers and Digital Techniques, vol. 132, Pt. E, no. 3, pp. 146-154, 1985 (with K. Nakajima and V.P. Krothapalli).

"t-Diagnosability for Fault Tolerant Parallel Systems", Microprocessing and Microprogramming, vol. 16, pp. 7-16, North Holland Publ. Co., Amsterdam, 1985.

"Reconfiguration in Microprocessor Schemes," Microprocessing and Microprogramming , vol. 13, pp. 315-323, North Holland Publ. Co., Amsterdam, 1984.

"Diagnosis of Microcomputer Systems by Triplet Assertion" Software and Microsystems , vol. 3, no. 5/6, pp. 111-121, IEE, London, 1984.

"Investigation and Design of a Controller of an Asynchronous System for Fault Tolerant Aircraft Control Using Hybrid Voting Techniques," Software and Microsystems, vol. 3, no. 1, pp. 11-18, IEE, London, 1984.

"Parallel Processing - An Alternative for the Future?," Journal of Capacity Management, vol. 1, no. 4, p. 382-391, Institute for Software Engineering, Sunnyvale, 1983 (with A.B. Kovaleski).

"Control of Locally-Testable Duplex System for Large Scale Implementation," Electronics Letters, vol. 19, no. 10, pp. 392-393, IEE, London, 1983.

"Analysis of Series Deviance in a Parallel State Transition Diagram and Applications to Fault Tolerant Computing," Microelectronics and Reliability, vol. 23, no. 5, pp. 963-980, Pergamon Press, Oxford, 1983 (with S. Ratheal).

"Reliability Analysis of Fault Tolerant Pipeline Ring Networks," Microelectronics and Reliability , vol. 23, no. 6, pp. 1055-1066, Pergamon Press, Oxford, 1983.

"Parallel/Series Dependency and Equivalence in Generalized Markov's Chains," Microelectronics and Reliability , vol. 23, no. 3, pp. 50l-507, Pergamon Press, Oxford, 1983.

"On the Imperfection of Replacement," Microelectronics and Reliability , vol. 23, no. 2, pp. 269-282, Pergamon Press, Oxford, 1983.

"Availability Analysis of N Module Parallel System with Common Memory, Central Controller and Distributed Software," Microelectronics and Reliability , vol. 22, no. 4, pp. 887-894, Pergamon Press, Oxford, 1982.

"Software Implemented Fault Tolerance: A Methodology," Microelectronics and Reliability , vol. 22, no. 4, pp. 873-886, Pergamon Press, Oxford, 1982 (with V. Obac Roda).

"Microcomputer Real Time Software Reliability and Fault Recovery" Microelectronics, and Reliability , vol. 22, no. 4, pp. 693-698, Pergamon Press, Oxford, 1982.

"Reliability Study of Duplex Hybrid Systems," Microelectronics and Reliability , vol. 22, no. 3, pp. 457-471, Pergamon Press, Oxford, 1982 (with V. Obac Roda and Md. M. Islam).

"An Automated Multi-Unit Animal Activity Monitoring System," IEEE Trans. on Biomedical Engineering , vol. BME-29, no. 8, pp. 625-626, 1982 (with O.J. Davies, V.M. B-D. Rumjanek and J. Morley) (abstract only).

"Availability Modelling of Ring Microcomputer Systems," Microelectronics and Reliability , vol. 22, no. 2, pp. 295-309, Pergamon Press, Oxford, 1982.

"Estimation of Total Errors in Software," Microelectronics and Reliability , vol. 22, no. 2, pp. 281-285, Pergamon Press, Oxford, 1982 (with Md. M. Islam).

"Reliability of Microprocessor System," Journal of Microcomputer Applications , vol. 4, no. 2, pp. 128-132, Liverpool, 1980 (with O.J. Davies).

"Microprocessor Based Simulator for Gamma Camera Image Processors," Medical and Biological Engineering and Computing , vol. 18, no. 4, pp. 479-480, IEE, London, 1980 (with O.J. Davies).

OTHER PUBLICATION ACTIVITY IN REFEREED JOURNALS, MAGAZINES AND PROFESSIONAL NEWSLETTERS

Guest Editor's Introduction, Special Issue on Defect Tolerance of Digital Systems, IEEE Transactions on Computers, vol. 48, no. 6, pp. 529-531, 2000 (with M.G. Sami).

Guest Editor's Introduction, Special Issue on Embedded Fault-Tolerant Systems, The Journal of Supercomputing. vol. 16, no. 1/2, pp. 5-6, Kluwer Academic Publishers, 2000 (with D. R. Avresky and B.W. Johnson).

Guest Editor's Introduction, Special Issue on Configurable Computing, IEEE Transactions on Computers, vol. 48, no. 6, pp. 553-555, 1999 (with J.L. Gaudiot).

Guest Editor's Introduction, Special Issue on DRAM Architecture and Test, IEEE Design and Test Magazine, vol. 16, no. 1, pp. 19-21, 1999 (with B. Cockburn and F.J. Meyer).

MTDT98 Report, Test Technology Newsletter, p. 12, Oct-Nov 1998.

Guest Editor's Introduction, Special Issue on Embedded Fault-Tolerant Systems, IEEE MICRO Magazine, vol. 18, no. 5, pp. 8-11, 1998 (with D.R. Avresky, K.E. Grosspietsch and B.W. Johnson).

Guest Editor's Introduction, Special Issue on FPGAs, IEEE Design and Test Magazine, vol. 15, no. 1, pp. 8-9, 1998.

Panelist on IEEE VLSI Test Symposium: Meeting the Quality Challenge, by Y. Savaria and A. Ivanov, IEEE Design and Test of Computers, vol. 13, no. 3, pp. 110-112, 1996.

Review of Post-Digital Electronics, by F.R. Petit, IEEE Circuits and Systems Magazine , vol. 6, no. l, pp. 19-20, 1984.

LIST OF PUBLICATIONS - HIGHLY REFEREED PROFESSIONAL CONFERENCES

"Testing Programmable Interconnect Systems: an Algorithmic Approach," Proc. 9th IEEE Asian Test Symposium, Taipei, November 2000 (with B. Liu and W.K. Huang) (accepted).

"Testing the Configurability of Dynamic FPGAs," Proc. IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Mt Fuji-Yamanashi, pp. 311-319, October 2000 (with N. Park and S.J. Ruiwale).

"On the Complexity of Switch Programming in Fault-Tolerant Configurable Chips," Proc. IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Mt Fuji-Yamanashi, pp. 125-133, October 2000 (with W. Shi and K. Kumar).

"Quality-effective Repair of Multi-chip Module Systems," Proc. IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Mt Fuji-Yamanashi, pp. 47-55, October 2000 (with N. Park and F.J. Meyer).

"Detection of Inter-Port Faults in Multi-Port Static RAMs," Proc. IEEE VTS, Montreal, pp. 297-302, May 2000 (with J. Zhao, S. Irrinki and M. Puri).

"A Novel Fault Tolerant Approach for SRAM-based FPGAs," Proc. IEEE Pacific Rim International Symposium on Dependable Computing, Hong Kong, pp. 40-44, December 1999 (with J. Xu, P. Si and W.K. Huang).

"A BIST TPG Approach to Interconnect Testing with the IEEE 1149.1 STD," Proc. 8th IEEE Asian Test Symposium, pp 95-100, Shanghai, November 1999 (with W. Feng, W.K. Huang and F.J. Meyer).

"Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs," Proc. 8th IEEE Asian Test Symposium, pp 357-362, Shanghai, November 1999 (with Y. Yu, J. Xu and W.K. Huang).

"Iddq Testing of Input/Output Resources of SRAM-based FPGAs," Proc. 8th IEEE Asian Test Symposium, pp 375-380, Shanghai, November 1999 (with L. Zhao and D.M.H. Walker).

"Stratified Testing of MultiChip Module Systems Under Uneven Known-good-yield" Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 192-200, Alberqueque, October 1999 (with N. Park).

"A Novel BIST TPG Method for Interconnect Testing Using the IEEE 1149.1 STD," Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp 112-120, Alberqueque, October 1999 (with F.J. Meyer and W. Feng).

"Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources," Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 368-376, Alberqueque, October 1999 (with W. Feng, X.T. Chen and F.J. Meyer).

"Good Processor Identification in Two-Dimensional Grids," Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 348-356, Alberqueque, October 1999 (with F.J. Meyer).

"Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects," Proc. IEEE Fault Tolerant Computing Symposium, pp. 130-137, Madison, June 1999 (with F.J. Meyer and W. Feng).

"Maximal Diagnosis of Interconnects of Random Access Memories," Proc. IEEE VTS, pp. 378-383, Dana Point, May 1999 (with F.J. Meyer and J. Zhao).

"Diagnosing Single Faults for Interconnects in SRAM Based FPGAs," Proc. IEEE ASP DAC, pp. 283-286, Hong Kong, January 1999 (with Y. Yu, J. Xu and W.K. Huang).

"Fault Detection in a Tristate System Environment," Proc. IEEE 7th Asian Test Symposium, pp. 253-258, Singapore, December 1998 (with W. Feng, W.K. Huang and F.J. Meyer).

"A Diagnosis Method For Interconnects in SRAM Based FPGAs," Proc IEEE 7th Asian Test Symposium, pp. 278-282, Singapore, December 1998 (with Y. Yu, J. Xu and W.K. Huang).

"Detection of Bridging Faults in Logic Resources of Configurable FPGAs Using Iddq," Proc. IEEE Int. Test Conf., pp. 1037-1046, Washington, October 1998 (with L. Zhao and D.M.H. Walker).

"On The Complexity of Sequential Testing in Configurable FPGAs," Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 164-172, Austin, October 1998 (with W. Feng, W.K. Huang and F.J. Meyer).

"A New Method for Testing EEPLA's" Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 146-154, Austin, October 1998 (with A. Munshi and F.J. Meyer).

"Fault Detection and Diagnosis of Interconnects of Random Access Memories," Proc. IEEE VLSI Test Symposium, pp. 42-47, Monterey, April 1998 (with J. Zhao and F.J. Meyer) .

"Bridging Fault Detection in FPGA Interconnects using I_DDQ." Proc. ACM Int. Symp. on FPGAs, pp. 95-104, Monterey, February 1998 (with L. Zhao and D.M. H. Walker).

"A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs," Proc. IEEE Asian Test Symposium, pp. 248-253, Akita, November 1997, (with W.K. Huang, M.Y. Zhang, and F.J. Meyer).

"Multiple Fault Detection in Logic Resources of FPGAs," Proc. IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 186-194, Paris, October 1997, (with W.K. Huang and F.J. Meyer).

"Testing of Programmable Logic Devices (PLD) with Faulty Resources," Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 76-84, Paris, October 1997 (with D.G. Ashen, F.J. Meyer and N. Park).

"Fault Tolerance of One-Time Programmable FPGAs with Faulty Routing Resources," Proc. IEEE Int. Conf. on Innovative Systems in Silicon, pp. 155-164, Austin, October 1997 (with F. J. Meyer, X.T. Chen and J. Zhao).

"An Efficient Multi-Way Algorithm for Balanced Partitioning of VLSI Circuits," Proc. IEEE ICCD, pp. 608-613, Austin, October 1997 (with X. Tan, J. Tong, P. Tan and N. Park).

"On the Multiple Fault Diagnosis of MINs: the Lower Bound and the CMOS Fault Model," Proc. Int. Conf. on Parallel Processing, pp. 350-353, Bloomingdale, August 1997 (with Y.N. Shen, X.T. Chen and S. Horiguchi).

"Using Virtual Links for Reliable Information Retrieval Across Point-to-Point Networks," Proc. IEEE Fault Tolerant Computing Symposium, pp. 216-225, Seattle, June 1997 (with F.J. Meyer, X.T. Chen and W.K. Huang).

"On the Fault Coverage of Interconnect Diagnosis," Proc. IEEE VLSI Test Symposium, pp. 101-107, Monterey, April 1997 (with X.T. Chen and F.J. Meyer).

"A Coloring Approach to the Structural Diagnosis of Interconnects," Proc. IEEE Int. Conf. on CAD, pp. 676-680, Santa Clara, November 1996 (with X.T. Chen).

"Layout-Driven Detection of Bridge Faults in Interconnects," Proc. IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 105-113, Boston, November 1996 (with T. Liu, X.T. Chen and J. Salinas).

"Modeling Quality Reduction of Multichip Module Systems due to Uneven Fault-Coverage and Imperfect Diagnosis," Proc. IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 168-176, Boston, November 1996 (with N. Park and S. S. Kim).

"Conformance Testing of Time Dependent Protocols," Proc. 2nd IEEE Int. Conf. of Eng. of Complex Computer Systems, pp. 257-263, Montreal, October 1996 (with N. Park, J. Salinas and U. Arunkumar).

"Array-Based Testing of FPGAs: Architecture and Complexity," Proc. IEEE Innovative Systems in Silicon Conference, pp. 249-258, Austin, October 1996 (with W.K. Huang and F.J. Meyer).

"Spare Cutting Approaches for Repairing Memories," Proc. IEEE Int. Conf. on Computer Design, pp. 106-111, Austin, October 1996 (with Y. N. Shen. and N. Park).

"On the Diagnosis of Programmable Interconnects: Theory and Applications," Proc. IEEE VLSI Test Symposium, pp. 204-209, Princeton, May 1996 (with X.T. Chen and W.K. Huang).

"A General Technique for Testing FPGAs," Proc. IEEE VLSI Test Symposium, pp. 450-455, Princeton, May 1996 (with W.K. Huang).

"Diagnosing Programmable Interconnect Systems for FPGAs," Proc. ACM International Symposium on FPGAs, pp. 100-106, Monterey, February 1996 (with D. Ashen, X.T. Chen and W.K. Huang).

"Accurate Communication Models for Task Scheduling in Multiprocessors," Proc. 7th IEEE Symp. on Paral. and Distr. Proc., pp. 524-529, San Antonio, October 1995 (with W.K. Huang, X.T. Chen and L. Bhuyan).

"Performance Evaluation of a Deferred Write Technique as a Recovery Technique in Client-Server DBMS," Proc. 12th Int. Conf. on Computer Comm., pp. 357-362, Seoul, August 1995 (with Y. Jeon).

"Diagnosing Multiple Bridge Faults in Baseline Multistage Interconnection Networks," Proc. Int. Conference on Parallel Processing, pp. I-131 - I-135, Oconomowoc, August 1995 (with V. Purohit, S. Horiguchi and J. H. Kim).

"A Submesh Allocation Scheme for Mesh-Connected Multiprocessor Systems, Proc. Int. Conference on Parallel Processing, pp. II-159 - II-163, Oconomowoc, August 1995 (with T. Liu, W.K. Huang and L. Bhuyan).

"A New Diagnosis Approach for Short Faults in Interconnects," Proc. IEEE Fault Tolerant Computing Symposium 25, pp. 331-339, Pasadena, June 1995 (with C. Feng and W.K. Huang).

"Diagnosis of Interconnects and FPICs using a Structured Walking-1 Approach," Proc. IEEE VLSI Test Symposium, pp. 256-261, Princeton, May 1995 (with T. Liu and J. Salinas).

"Fault Tolerant Sorting in SIMD Hypercubes," Proc. IEEE International Parallel Processing Symposium, pp. 312-318, Santa Barbara, April 1995 (with A. Mishra, Y. Chang and L. Bhuyan).

"Testing of Uncustomized Segmented Channel FPGAs," Proc. ACM International Symposium on FPGAs, pp. 125-131, Monterey, February 1995 (with T. Liu and W.K. Huang).

"Optimal Switching Networks for WSI Architectures with Fault Tolerant Path Routing," Proc. IEEE Int. Conference on Wafer Scale Integration, pp. 153-162, San Francisco, January 1995 (with T. Liu).

"Yield Analysis of Fault Tolerant Multichip Module Systems for Massively Parallel Computing," Proc. IEEE Int. Conference on Wafer Scale Integration, pp. 308-317, San Francisco, January 1995 (with S.S. Kim).

"Matrix Multiplication on the MasPar Using Distance Insensitive Communication Schemes," Proc. 3rd IEEE Int. Symp. on Parallel Arch., Algorithms and Networks (ISPAN), pp. 358-365, Kanazawa, December 1994 (with X. Sun).

"A Divide-and-Conquer Methodology for System-Level Diagnosis of Processor Arrays," Proc. 6th IEEE Symp. on Parallel and Distr. Processing, pp. 352-359, Dallas, December 1994 (with C. Feng and L. Bhuyan).

"Rank Ordering Filtering on an Array with Faulty Processors," Proc. Int. Conf. on Parallel Proc., St. Charles, pp. I-236-241, August 1994 (with J. Salinas).

"FSM Test: Functional Test Generation for Sequential Circuits," Proc. 4th IEEE European Test Conference, Paris, February 1994 (with G. Buonanno, F. Fummi, D. Sciuto and J. Salinas) (poster presentation only).

"Optimal Reconfiguration of WSI Multipipeline Arrays," Proc. IEEE Int. Conference on Wafer Scale Integration, pp. 143-152, San Francisco, January 1994 (with J. Wall, J. Salinas and C. Feng).

"Diagnosis of Reconfigurable Two-Dimensional Arrays Using a Scan Approach," Proc. IEEE Int. Conference on Wafer Scale Integration, pp. 179-187, San Francisco, January 1994 (with J. Salinas).

"An Adaptive System-Level Diagnosis Approach for Hypercube Multiprocessors," Proc. 5th IEEE Symp. on Parallel and Distr. Proc., pp. 460-467, Dallas, Dec. 1993 (with C. Feng and L. Bhuyan).

"GID - Testable Two-Dimensional Sequential Arrays with Self-Testing," Proc. IEEE Asian Test Symposium, pp. 225-229, Beijing, October 1993 (with W.K. Huang and M. Lu).

"On the Minimal Test Set for Single Fault Location," Proc. IEEE EURO-DAC, pp. 265-270, Hamburg, September 1993 (with X. Sun and D. Sciuto).

"Emulating Reconfigurable Arrays for Image Processing Using the MasPar Architecture," Proc. Int. Conf. on Parallel Processing, pp. III-141-147, St. Charles, August 1993, (with J. Salinas).

"An Adaptive System-Level Diagnosis Approach for Mesh Connected Multiprocessors," Proc. Int. Conf. on Parallel Processing, pp. III-153-157, St. Charles, August 1993, (with C. Feng and L. Bhuyan).

"On the Testability of FFT Arrays," Proc. 3rd IEEE European Test Conference, pp. 219-229, Rotterdam, April 1993.

"On the Design for Testability of Sequential Circuits," Proc. IEEE VLSI Test Symposium, pp. 147-150, Atlantic City, April 1993 (with X. Sun).

"Testing Constant-Geometry FFT Arrays for Wafer Scale Integration," Proc. IEEE Int. Conf. on WSI, pp. 203-212, San Francisco, January 1993 (with J. Salinas and C. Feng).

"An Approach for Reducing the Programming Cost of Soft Switches in Reconfigurable WSI Arrays," Proc. IEEE Int. Conf. on WSI, pp. 233-242, San Francisco, January 1993 (with T. Liu).

"On The Verification and Validation of Protocols with High Fault Coverage Using UIO Sequences," Proc. 11th IEEE Symp. on Reliable Distributed Systems, pp. 196-203, Houston, October 1992 (with X. Sun and Y.N. Shen).

"Detection of Multiple Faults in CMOS Circuits using a Behavioral Approach," Proc. IEEE VLSI Test Symposium, pp. 188-193, Atlantic City, April 1992 (with Y.-N. Shen).

"On Self-Testing of Array Systems," Proc. IEEE Int. Conf. on WSI, pp. 321-330, San Francisco, January 1992 (with W-K Huang).

"Reconfiguration of Two-Dimensional VLSI Arrays by Time-Redundancy," Proc. IEEE Int. Conf. on WSI, pp. 210-219, San Francisco, January 1992 (with S. Yurttas).

"On a New Approach for Enhancing the Fault Coverage of Conformance Testing of Protocols," Proc. 3rd IEEE Symposium on Parallel and Distributed Processing, pp. 428-435, Dallas, December 1991 (with Y. -N Shen and H.H. Kari).

"Protocol Conformance Testing by Discriminating UIO Sequences," Proc. 11th IFIP Int. Symp. on Protocol Spec., Testing, and Ver., Stockholm, June 1991 (with D. Sciuto, X. Sun and Y.-N. Shen).

"Concurrent Error Detection and Fault Location in Reconfigurable WSI Structures for FFT Computation," Proc. IEEE Int. Conf. on WSI, pp. 47-53, San Francisco, January 1991 (with J. Muzio) .

"On the Testability of Array Structures for FFT Computation," Proc. 2nd IEEE Symp. on Parallel and Distr. Processing, pp. 519-522, Dallas, December 1990 (with J. Muzio and Y.-N. Shen).

"Evaluation and Improvement of Fault Coverage for Verification and Validation of Protocols," Proc. 2nd IEEE Symp. on Parallel and Distr. Processing, pp. 200-207, Dallas, December 1990 (with Y.-N. Shen and D. Sciuto).

"A Routing Algorithm For Harvesting Multipipeline Arrays with Small Intercell and Pipeline Delays," Proc. IEEE Int. Conf. on CAD, pp. 2-5, Santa Clara , November 1990 (with P. Koo and D. Sciuto).

"Multiple Fault Detection and Location in WSI Baseline Interconnection Networks," Proc. IEEE Int. Conference on WSI, pp. 145-151, San Francisco, January 1990 (with C. Feng and W-K Huang).

"Testing Wafer Scale Arrays: Constant Testability Under Multiple Faults," Proc. IEEE Int. Conf. on WSI, pp. 251-257, San Francisco, January 1990 (with D. Sciuto).

"Fault Detection in a Testable PLA with Low Overhead for Production Testing," Proc. IEEE Int Conf. on CAD, pp. 566-569, Santa Clara, November 1989 (with Y.-N. Shen).

"Location and Identification for Single and Multiple Faults in Testable Redundant PLAs for Yield Enhancement," Proc IEEE Int. Test Conference, pp. 670-678, Washington, August 1989 (with Y.-N. Shen).

"Protocol Conformance Testing By Multiple UIO Sequences," Proc. 9th IFIP Int. Symp. on Protocol. Spec., Testing and Ver., Twente, June 1989 (with Y.-N. Shen and A.T. Dahbura).

"On a Tapered Floating Point System," Proc 9th IEEE Symp. Comp. Arith., pp. 2-9, Santa Monica, September 1989 (with A.M. Azmi).

"A Compared Evaluation of Classes of Reconfiguration Strategies for Fault Tolerance in VLSI Array Processor Architectures," Proc. IEEE Int. Conf. on Systolic Arrays, in Systolic Array Processors, Edited by J. McCanny, J. McWirther and E. Swartzlander, pp. 557-566, Dublin, Prentice Hall, May 1989 (with D.Sciuto).

"Minimizing the Cost of Repairing WSI Memories," Proc. IEEE Int. Conf. on WSI, pp. 183-192, San Francisco, January 1989 (with W-K Huang).

"Array Partitioning: A Methodology for Reconfigurability and Reconfiguration Problems," Proc. IEEE ICCD: VLSI In Comp. and Processors, pp. 564-567, Rye Brook, October 1988 (with D. Sciuto and F. Distante).

"Approaches for the Repair of VLSI/WSI RRAMs by Row/Column Deletion," Proc. IEEE Fault Tolerant Computing Symposium 18, pp. 342-347, Tokyo, June 1988 (with W-K Huang).

"New Approaches for the Reconfiguration of Two-Dimensional VLSI Arrays Using Time-Redundancy," Proc. IEEE Real-Time Systems Symposium, pp. 212-221, Huntsville, December 1988 (with S. Yurttas).

"A Technique for Reconfiguring Two Dimensional VLSI Arrays," Proc. IEEE Real Time Systems Symp., pp. 44-53, San Jose, December 1987 (with R. Stefanelli and D. Sciuto).

"Reconfiguration of VLSI Arrays: A Covering Approach," Proc IEEE Fault Tolerant Computing Symposium 17, pp. 251-256, Pittsburgh, July 1987 (with R. Negrini, M.G. Sami, R. Stefanelli).

"Predicting Fault Coverage for Random Testing of Combinational Circuits," IEEE Int. Test Conference, pp. 843-848, Washington, September 1987 (with W-K Huang and M. Lightner).

"An Architecture and an Interconnection Scheme for Time-Sliced Buses in Real-Time Processing", Proc. IEEE Real-Time System Symposium, pp. 20-27, New Orleans, December 1986 (with A. Kovaleski and S. Ratheal).

"On a Multiprocessor System with Dynamic Redundancy," Proc. IEEE Real Time Systems Symposium, pp. 3-12, San Diego, November 1985.

"Diagnosable Systems for Fault Tolerant Computing," Proc. IEEE Fault Tolerant Computing Symposium 15, pp. 42-47, Ann Arbor, June 1985.

"Fault Identification Algorithms for VLSI Systems" Proc. ICCD Int. Conf. on Comp. Design: VLSI in Computers, pp. 693-696, Port Chester, October 1985, (with C-L Wey).

LIST OF PUBLICATIONS - OTHER REFEREED CONFERENCE PROCEEDINGS

"Reliable Computing through N-Modular-Redundancy-on-Demand," Proc. IEEE International Workshop on Embedded Fault-Tolerant Systems, Paper III-1 (28 pages) Washington, September 2000 (with M. Hashimi).

"A Location Counter Strategy for Fault-Tolerance in a Wireless Mobile Environment," Proc. IEEE International Workshop on Embedded Fault-Tolerant Systems, Paper VI-1 (25 pages) Washington, September 2000 (with Y. An and N. Park).

"Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models," Proc. IEEE Int. Workshop on MTDT, pp. 14-19, San Jose, August 2000 (with J. Zhao and F.J. Meyer).

"Testing and Evaluating the Quality-Level of Stratified Multichip Module Instrumentation," Proc. 17th IEEE Instr. and Measurament Technology Conf. pp. 1578-1583, Baltimore, May 2000 (with V. Piuri and N. Park).

"Detecting Inter-Port Faults in Multi-Port Memories," Proc. 9th IEEE North Atlantic Test Workshop, pp. 32-37, Gloucester, May 2000 (with J. Zhao, M. Puri and S. Irrinki).

"Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping," Proc.. IPDPS2000 Workshops RAW2000, 7th Reconfigurable Architectures Workshop, pp. 951-958, Springer-Verlag, Cancun, May 2000 (with F.J. Meyer and W. Feng).

"On the Defect Level of Multichip Module Systems with Repair at Assembly," 8th Annual NASA Symposium on VLSI Design, pp 7-1-1;7-1-11, Alberquerque, October 1999 (with N. Park).

"Interconnect Diagnosis of Bus-Connected Multi-RAM Systems," Proc. IEEE International Workshop on Memory Technology Design and Testing, pp. 40-47, San Jose, August 1999 (with F.J. Meyer and J. Zhao).

"Diagnosing Interconnects of Random Access Memories," Proc. 8th IEEE North Atlantic Test Workshop, pp. 56-61, West Greenwich, May 1999 (with J. Zhao and F.J. Meyer).

"Adaptive Approaches For Fault Detection and Diagnosis of Interconnects of Random Access Memories," Proc. IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 110-116, San Jose, August 1998 (with J. Zhao and F. J. Meyer).

"Repair of Memory Arrays by Cutting," Proc. IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 124-129, San Jose, August 1998 (with N. Park).

"Rapid In-Place Reconfiguration of One-Time Programmable FPGAs," Proc. IEEE Int. Workshop on Embedded Fault-Tolerant Systems, p. 122, Boston, May 1998 (with X.T. Chen, F.J. Meyer, W. Feng and J. Zhao) (abstract only).

"Testing Memory Modules in SRAM-Based Configurable FPGAs," Proc. IEEE Int. Workshop on Memory Technology, Design and Testing, pp 79-86, San Jose, August 1997 (with W.K. Huang, F.J. Meyer and N. Park).

"Design and Tools for Fault Tolerant Reconfigurable Systems using FPGAs," Proc. IEEE Int. Workshop on Embedded Fault Tolerant Systems, Dallas, Sept 1996 (with F.J. Meyer) (abstract only).

"Constant Optimal Testability of Two-Dimensional Combinational Arrays," Proc. Int. Workshop on CAD, Test and Evaluation for Dependability, pp. 79-84, Beijing, June 1996 (with M.Y. Zhang, W.K. Huang and X. Chen).

"Diagnosis of Interconnects by Computational Geometry," Proc. Pacific Rim International Symposium on Fault Tolerant Systems, pp. 2-7, Irvine, December 1995 (with Y.N. Shen, J. Salinas and X.T. Chen).

"Repair Algorithms for Mirrored Disks Systems," Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 216-224, Lafayette, November 1995 (with H. H. Kari, H. Saikkonnen and S.S. Kim).

"An Improved Approach to Fault Tolerant Rank Order Filtering on a SIMD Mesh Processor," Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 137-145, Lafayette, November 1995 (with N. Vaidya and J.H. Kim).

"A Row-Based FPGA for Single and Multiple Stuck-at Fault Detection," Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 225-233, Lafayette, November 1995 (with X.T. Chen, W.K. Huang and X. Sun).

"Interconnect Diagnosis," Proc. 6th Symposium on Fault Tolerant Computers (Brazilian Computer Society), pp. 3-4, Canela, August 1995 (abstract only).

"Field Programmable Gate Arrays: the Next Generation Technology for Cost Effective Fault Tolerant Computing," Proc. 6th Symposium on Fault Tolerant Computers (Brazilian Computer Society), pp. 221-222, Canela, August 1995 (abstract only).

"Modeling Testing Strategies for Yield Enhancement of Multichip Module Systems," Proc. 2nd ISSAT Int. Conf. on Reliability and Quality in Design, pp. 269-273, Orlando, March 1995 (with S.S. Kim).

"Scheduling Policies for Fault Tolerance in a VLSI Processor," Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 1-9, Montreal, October 1994 (with Y. N. Shen, H. H. Kari and S.S. Kim).

"On Soft Switch Programming for Reconfigurable Array Systems," Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 203-211, Montreal, October 1994 (with T. Liu).

"An Approach for UIO Generation for FSM Verification and Validation," Proc. IEEE ISCAS, pp 4.303-4.306, London, May 1994 (with Y.N. Shen and D. Schin).

"Detecting Latent Sector Faults in Modern SCSI Disks," MASCOTS'94: Proc. Int. Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Society for Computer Simulation (SCS), pp. 403-404, Durham, January 1994 (with H.H. Kari and H. Saikkonen).

"Detection of Defective Media in Disks," Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 49-55, Venice, October 1993 (with H.H. Kari and H. Saikkonen).

"On the Reconfigurable Operation of Arrays with Defects for Image Processing," Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 88-95, Venice, October 1993 (with J. Salinas).

"On The Methods to Detect Latent Sector Faults of a Disk Subsystem" MASCOTS'93: Proc. Int. Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Society for Computer Simulation (SCS), vol. 25, no. 1, pp. 317-322, San Diego, January 1993 (with H.H. Kari and H. Saikkonen).

"CAPTIONALS, a Computer Aided Testing Environment for the Verification and Validation of Communication Protocols," Mission Safety Critical Systems: Research and Applications, RISC, Houston, October 1992 (with C. Feng, X. Sun and Y.N. Shen).

"Concurrent Built-in Self-Test with Reduced Fault Latency" IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 199-212, Hidden Valley, November 1991 (with Y.-N. Shen).

"Multiple Stuck-At Fault Detection in CMOS Combinational Gates," Proc. Euromicro 91, The 17th Symposium on Microprocessing and Microprogramming, pp. 775-782, August 1991 (with G. Buonanno, D. Sciuto and Y.-N. Shen).

"An Approach for On-Line Repair and Yield Enhancement of VLSI/WSI Redundant Memories," Proc. IEEE Comp. Euro, pp. 685-689, Bologna, May 1991 (with Y.-N. Shen).

"Testability Conditions for Linear Sequential Arrays," Proc. IEEE Annual Phoenix Conf. on Comp. and Comm. pp. 63-70, Phoenix, March 1991 (with D. Sciuto and G. Buonanno).

"Generalized Approaches and Algorithms for Reconfigurable VLSI/WSI Systems," Proc. IEEE/IFIP Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 188-216, Grenoble, November 1990, (with Y.-N. Shen and D. Sciuto).

"Constant Testability for Single Fault Detection in Two-Dimensional Systolic Array Structures for Matrix Multiplication," Proc. IEEE ISCAS, pp. 2728-2731, New Orleans, May 1990 (with D. Sciuto and W-K Huang).

"C-Testability of Two-Dimensional Sequential Arrays," Int. Conf. on Semicond. and IC Technology, Beijing, October 1989 (with W-K Huang).

"On a Testable PLA Design for Production," Proc. 4th Workshop on IC Testing, pp. 89-122, Victoria, October 1989 (with Y.-N. Shen) (invited).

"On the Minimum Repair Cost for VLSI/WSI Memory Chips with Redundancy," Joint Symposium on Fault-Tolerant Computing, pp. 43-49, Chongqing, July 1989 (with W.-K. Huang).

"An Approach for Single Fault Detection and Location in Baseline Interconnection Networks with a Constant Number of Tests," Joint Symposium on Fault-Tolerant Computing, pp. 186-191, Chongqing, July 1989 (with W.-K. Huang).

"On Testable Redundant PLAs for WSI Implementation," Proc. 3rd IFIP Workshop on WSI, Como, June 1989 (with Y.-N. Shen).

"Techniques for Repairability/Unrepairability Detection For Yield Enhancement of WSI Redundant Memories," Proc. 3rd IFIP Workshop on WSI, Como, June 1989 (with Y.-N. Shen).

"Real-Time Reconfiguration of Two-Dimensional VLSI Arrays," Proc. Euromicro Int. Workshop on Real-Time Systems, pp. 217-225, Como, Italy 1989 (with D. Sciuto).

"New Conditions for Testability of Two-Dimensional Bilateral Arrays," Proc. IEEE Int. Conf. on Systolic Arrays, pp. 495-504, San Diego, May 1988 (with D. Sciuto).

"Orthogonal Mapping: A Reconfiguration Strategy for Fault Tolerant VLSI/WSI 2-D Arrays," Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 7.4.1-7.4.12, Springfield, October 1988 (with D. Sciuto and L. Jervis).

"Linear Testability Conditions for Two-Dimensional Arrays" Proc. Euromicro 88, The 14th Symposium on Microprocessing and Microprogramming, in Microprocessing and Microprogramming, vol. 25, no. 1, pp. 85-90, Zurich, August 1988 (with D. Sciuto).

"Optimum Reconfiguration of Arrays in a ULSI Environment," 3rd Int. Conf. on Supercomputing, vol. 3, pp. 272-280, Boston, May 1988 (with M.G. Sami and R. Stefanelli).

"Design for C-Testability of Two-Dimensional Bilateral Arrays" 11th Annual IEEE Workshop on Design for Testability, Vail, April 1988 (with W-K Huang)(presentation only).

"Testability Conditions for two-Dimensional Bilateral Arrays," Proc. IEEE ISCAS, pp. 565-568, Helsinki, June 1988 (with D. Sciuto).

"Repair of Redundant Memories by Reduced Covering," Proc. IEEE ISCAS, pp. 205-208, Helsinki, June 1988 (with D.Sciuto).

"A Technique for Fault Detection in C-Testable Orthogonal Iterative Arrays," Proc. IEEE CompEuro, Brussels, pp. 203-212, April 1988 (with W-K Huang).

"Functional Testing of Array Processors," Proc. IEEE CompEuro, Brussels, pp. 314-323, April 1988 (with D. Sciuto).

"Design and Analysis of C-Testable Arrays," Proc. IFIP Workshop on WSI, London, September 1987 (with W-K Huang and D. Sciuto).

"On Fault Coverage of Random Testing," 10th Annual IEEE Workshop on Design for Testability, Vail, April 1987 (with W-K Huang and M. Lightner) (presentation only).

"Functional Reconfiguration in Fixed-Size VLSI Arrays," Proc. IEEE ISCAS , pp. 386-389, Philadelphia, May 1987 (with D. Sciuto and R. Stefanelli).

"Efficient, yet Simple Algorithms for Repairing Redundant RAMS," Proc. IEEE ISCAS , pp. 871-874, Philadelphia, May 1987, (with C-L Wey).

"Reconfiguration of VLSI Arrays: An Index Mapping Approach," Proc. IEEE CompEuro 87 VLSI and Computers, pp. 60-65, Hamburg, May 1987 (with M.G. Sami and R. Stefanelli) (invited).

"Reconfiguration in WSI Arrays using Minimum Spanning Trees," Proc. IEEE CompEuro 87, VLSI and Computers, pp. 547-550, Hamburg, May 1987 (with D. Sciuto).

"Analysis and Design of Repairable PLAs," Proc. IEEE CompEuro 87, VLSI and Computers, pp. 363-366, Hamburg, May 1987 (with C-L Wey).

"Diagnosis by Comparison with Faulty Comparators," Proc. 12th Symp. on Microprocessing and Microprogramming, pp. 271-274, Venice, September 1986.

"A Functional Methodology for Array Testing," Proc. 9th Annual IEEE Workshop on Design for Testability, Vail, April 1986 (with D. Sciuto) (presentation only).

"On the Repair of Programmable Logic Arrays," Proc. IEEE ISCAS 86, pp. 649-652, San Jose, May 1986 (with C-L Wey) (invited).

"On a New Decision Process for the t-Diagnosis of an Analog System" Proc. IEEE ISCAS 86, pp. 1255-1256, San Jose, May 1986 (with C-L Wey).

"Two Algorithms for Delay-Constrained Reconfiguration of WSI Arrays," Proc. IFIP Workshop on WSI, Grenoble, March 1986 (with D. Sciuto) (invited)(presentation only).

"Diagnosis and Fault Identification Algorithms for Large Scale Computing Systems" Proc. 1st IEEE Int. Conf. on Supercomputing Systems, pp. 404-413, St. Petersburg, December 1985 (invited).

"Optimal Redundancy Management of Multi-Processor Systems for Supercomputing Applications," Proc. 1st IEEE Int. Conf. on Supercomputing Systems, pp. 414-422, St. Petersburg, December 1985.

"On Undirected Graph Diagnostic Models for VLSI Systems," Proc. 8th Annual Workshop on Design for Testability, pp. 4-5, Beaver Creek, April 1985.

"Fault Identification in t-Diagnosable Systems for Fault Tolerant Computation," Proc. IEEE Int. Symposium on Circuits and Systems, pp. 1539-1541, Kyoto, June 1985.

"On the Equivalence of Fault Identification in Undirected Graph Diagnostic Models and a Transitive Closure," Proc. 19th Conf. on Information Sciences and Systems, The Johns Hopkins University, Baltimore, pp. 74-75, March 1985 (abstract only).

"Fault Tolerance and t-Diagnosis: Affinities and Differences," Proc. l9th Conf. on Information Sciences and Systems, The Johns Hopkins University, Baltimore, pp. 77-79, March l985.

"A Testbed Environment for High Performance Computer System Design," Proc. IEEE 4th Annual Phoenix Conf. on Computers and Communications, pp. 523-527, Phoenix, March 1985. (with S. Ratheal).

"Models and Algorithms for t-Fault-Diagnosable Systems in Distributed Processing," 27th Midwest Symposium on Circuits and Systems, pp. 647-649, Morgantown, June 1984 (invited).

"On the Application of t-Diagnosability to Fault Tolerant High Throughput Computation," Proc. 18th Conf. on Information Sciences and Systems, pp. 260-264, Princeton University, March 1984.

"t-Diagnosability and Fault Tolerance: System Organization for Parallel and Real Time Processing," Computers in Comm. and Control, D.A. Duce, Editor, Proc. Eurocon 84, 6th European Conf. on Electrotechnics, pp. 102-104, Brighton, September 1984.

"Performance/Efficiency Evaluation of Parallel Multiprocessor Restructurable Systems Using Analytic Modelling Techniques," Proc. IEEE 3rd Annual Phoenix Conference on Computers and Communications, pp. 72-79, Phoenix, March 1984.

"Performability Evaluation of Static and Dynamic Duplex Systems by Queueing Methods," Computers in Comm. and Control, D. A. Duce, Editor, Eurocon 84, 6th European Conf. on Electrotechnics, Brighton, September 1984.

"A Synchronous Parallel System with Interconnected Time Multiplexed Buses," Proc. 18th Conf. on Information Sciences and Systems, pp. 258-259, Princeton, March 1984 (with A.B. Kovaleski) (abstract only).

"Testable Large Scale Computer Networks: Analysis and Simulation of Reconfiguration Algorithms," Proc. IEEE 3rd Annual Phoenix Conf. on Computers and Communications, pp. 80-86, Phoenix, March 1984 (with S. Ratheal).

"Diagnosis and Performance of Large Scale Duplex Hybrid Systems," Proc. 27th Midwest Symposium on Circuits and Systems, pp. 650-653, Morgantown, June 1984.

"Intelligent Adaptability in Large Scale Systems: Distributed Networks for Triplet Testing," Proc. IEEE Int. Symp. on Circuits and Systems, pp. 714-717, Montreal, May 1984 (with S. Ratheal).

"Analysis and Design of Static and Dynamic Fault Tolerant Ring System," Proc. 21st Annual Allerton Conf. on Communications, Control and Computing, pp. 822-831, Urbana-Champaign, October 1983 (with V. Obac Roda and O.J. Davies).

"Fault Proof and Design of a Control Unit for a Fault Tolerant System in a Fly-By-Wire Aircraft," Proc. Seventeenth Asilomar Conference on Circuits, Systems and Computers, pp. 286-290, Pacific Grove, October 1983 (with S. Ratheal).

"Evaluation of a Bus Network Parallel Processing Architecture," SIAM 1983 Conf. on Parallel Processing for Scientific Applications, Fall Meeting, Norfolk, November 1983 (with A. B. Kovaleski and S. Ratheal)(abstract only).

"Soft Testbed: A First Step to Distributed Systems Design and Testing," IEEE Computer Society Workshop on Laboratories for Reliable Systems Research , Langley, April 1983 (with S. Ratheal)(abstract and presentation only).

"Efficient Testing for Analog and Digital Electronic Systems: A Highly Desirable Feature for Future Technology," Proc. 1983 IEEE Conf. on Technology for an Efficient Tomorrow, p. 180, Houston, April 1983 (with K. Nakajima and R. Saeks)(abstract only).

"Generalized Modelling of Centralized and Distributed Restructuring for Different Classes of Faults: Performance and Profits and Analysis," Proc. 1983 IEEE Conf. on Technology for an Efficient Tomorrow, pp. 181-186, Houston, April 1983 (with S. Ratheal).

"Analysis and Simulation of Triplet Configurations for Network Testability," Proc. 17th Conf. on Information Sciences and Systems, pp. 649-653, The Johns Hopkins University, Baltimore, March 1983 (with S. Ratheal).

"Control and Verification of Fault Tolerant Procedures for Duplex Hybrid System Operation," Proc. 17th Conf. on Information Sciences and Systems , pp. 664-668, The Johns Hopkins University, Baltimore, March 1983 (with H.E. Harvey).

"Generalized Modelling of Testing and Reconfigurability: System Activities for Improved Performance," Proc. 5th Int. Conf. on Comp. Capacity Management , pp. 169-178, New Orleans, April 1983 (with S. Ratheal).

"Analysis and Implementation of System Procedures for Software Implemented Fault Tolerant Microcomputer Schemes," Proc. IEEE 2nd Annual Phoenix Conference, pp. 123-127, Phoenix, March 1983 (with O.J. Davies, V. Obac Roda, and H.E. Harvey).

"Characterization of a High Available Duplex Large Scale System by Cell Partition," Proc. 20th Annual Allerton Conf. on Communications, Control and Computing, pp. 987-995, Urbana-Champaign, October 1982 (with O.J. Davies).

"On System Diagnosability Using Triplet Assertion," Proc. IEEE Large Scale Systems Symposium, pp. 264-268, Virginia Beach, October 1982 (with O.J. Davies).

"An Automated Multi-Unit Animal Activity Monitoring System," Proc. 4th Annual Conf. of the IEEE Eng. in Medicine and Biology Soc., Frontiers of Computer in Medicine (COMPMED 82), Conf. Proc. vol. 4, September 1982, Philadelphia, (with O.J.Davies, V.M. B-D. Rumjanek and J. Morley).

"Availability Analysis of Fault Tolerant Microcomputer Systems with Periodic Preventive Replacement," Proc. Euromicro 82, 8th Symposium on Microprocessing and .i Microprogramming," pp. 185-191, Haifa, September 1982 (with O.J. Davies).

Software Implementation of a Disagreement Detector for Duplex Hybrid Systems," Proc. Eurocon 82, Electrotechnics Conference, pp. 673-678, Editors E. Langer and J. Multoft, Copenhagen, North Holland Publ. Co., June 1982 (with V. Obac Roda).

"Microcomputer Schemes for Reliability and Faults Tolerance in Data Acquisition Applications," Proc. of the 28th International Scientific Congress on Electronics, pp. 484-489, Roma, March 1981.

"An Automated Activity Monitoring System for EAE Studies," Proc. Multiple Sclerosis Society Annual Meeting, vol. 2, London, February 1981, (with O.J. Davies, V.M. Rumjanek, and J. Morley).

"Toward More Reliable Microcomputer Systems," Proc. IEE Colloquium on Reliable Systems for Microprocessor Control , Digest 69, pp. 1-3, London, November 1980 (with O.J. Davies).

"Reliability in Microprocessor System," Proc. 4th Annual Microprocessor Conference, University of Liverpool, April 1980 (with O.J. Davies).

"Portable Pulmonary Function Data Logger," Proc. 9th Annual Microprocessor Conference, Biological Engineering Society, Sheffield, April 1979 (with O.J. Davies) (invited).

"A Portable Digital Recorder/Processor for Gamma Camera Images", Proc. Physiological Society Annual General Meeting , London, March 1979 (with O.J. Davies) (invited).